The implementation of a 2-core multi-threaded itanium-family processor

Naffziger, Samuel; Stackhouse, B.; Grutkowski, T.

doi:10.1109/isscc.2005.1493929

Cited by 73 publications

(45 citation statements)

References 4 publications

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“…Moreover, specifically designed benchmarks, named micro-benchmarks, are needed in several situations. For instance, they have been used to reverse engineer structure latencies [24] or branch organization [37,45], to evaluate performance, power or thermal efficiency [15,22,28,38] or to generate and calibrate models [8,9,12].…”

Section: Related Workmentioning

confidence: 99%

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Bertran

Buyuktosunoglu

Gupta

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon modeling and/or diagnostic postsilicon measurement based analysis are increasingly cumbersome and error prone. This is especially true of energy-related characterization studies. In this paper, we take the position that automated micro-benchmarks generated with particular objectives in mind hold the key to obtaining accurate energy-related characterization. As such, we first present a flexible micro-benchmark generation framework (MicroProbe) that is used to probe complex multi-core/multithreaded systems with a variety and range of energy-related queries in mind. We then present experimental results centered around an IBM POWER7 CMP/SMT system to demonstrate how the systematically generated micro-benchmarks can be used to answer three specific queries: (a) How to project application-specific (and if needed, phase-specific) power consumption with component-wise breakdowns? (b) How to measure energy-per-instruction (EPI) values for the target machine? (c) How to bound the worst-case (maximum) power consumption in order to determine safe, but practical (i.e. affordable) packaging or cooling solutions? The solution approaches to the above problems are all new. Hardware measurement based analysis shows superior power projection accuracy (with error margins of less than 2.3% across SPEC CPU2006) as well as maxpower stressing capability (with 10.7% increase in processor power over the very worst-case power seen during the execution of SPEC CPU2006 applications).

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Section: Related Workmentioning

confidence: 99%

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Bertran

Buyuktosunoglu

Gupta

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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“…2 And this excludes the additional power required from the increased resource use resulting from improvements targeting instruction-and thread-level parallelism.…”

Section: Power Efficiencymentioning

confidence: 99%

Montecito: A Dual-Core, Dual-Thread Itanium Processor

2005

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“…In fact, the limitations on power dissipation imposed by packaging constraints have become so paramount that performance metrics are now typically measured per unit power [1]. At the chip scale, the trend toward multicore architectures and chip multiprocessors (CMPs) for driving performance-per-watt by increasing the number of parallel computational cores is dominating new commercial releases [2], [3], [4], [5], [6]. With the future path clearly toward further multiplication of the on-chip processing cores, CMPs have begun to essentially resemble highly parallel computing systems integrated on a single chip.…”

Section: Introductionmentioning

confidence: 99%

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

Shacham¹,

Bergman

Carloni

2008

IEEE Trans. Comput.

836

451

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Abstract-The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intrachip and off-chip communication on the overall power budget. The low loss properties of optical waveguides, combined with bit-rate transparency, allow for a photonic interconnection network that can deliver considerably higher bandwidth and lower latencies with significantly lower power dissipation than an interconnection network based only on electronic signaling. We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation. We introduce a novel hybrid microarchitecture for NoCs that combines a broadband photonic circuit-switched network with an electronic overlay packet-switched control network. This design leverages the strength of each technology and represents a flexible solution for the different types of messages that are exchanged on the chip; large messages are communicated more efficiently through the photonic network, while short messages are delivered electronically with minimal power consumption. We address the critical design issues including topology, routing algorithms, deadlock avoidance, and path-setup/teardown procedures. We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed design idea, as well as a comparative power analysis of a photonic versus an electronic NoC. Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs.

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The implementation of a 2-core multi-threaded itanium-family processor

Cited by 73 publications

References 4 publications

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Montecito: A Dual-Core, Dual-Thread Itanium Processor

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

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