The important challenge to extend spacer DP process towards 22nm and beyond

Oyama, Kenichi; Nishimura, Eiichi; Kushibiki, Masato; Hasebe, Kazuhide; Nakajima, Shigeru; Murakami, Hiroki; Hara, Arisa; Yamauchi, Shohei; Natori, Sakurako; Yabe, Kazuo; Yamaji, Tomohito; Nakatsuji, Ryota; Yaegashi, Hidetami

doi:10.1117/12.845970

Cited by 17 publications

(8 citation statements)

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“…As a consequence, the double patterning process has become the standard technology for diverse types of semiconductor devices as a means of extending the life of 193-nm exposure technology. We have previously reported on the extendibility and versatility of the double patterning process, from pitch-doubling by self-aligned double patterning (SADP) [1] to pitch-quadrupling by self-aligned quadruple patterning (SAQP) [2]. We also reported on the effectiveness of SADP technology for increasing resolution in hole patterns.…”

Section: Introductionmentioning

confidence: 89%

Extendibility of self-aligned type multiple patterning for further scaling

et al. 2013

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Section: Introductionmentioning

confidence: 89%

Extendibility of self-aligned type multiple patterning for further scaling

et al. 2013

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“…True Maskless Litho (ML2) using massively parallelization of beams proposed by companies like MAPPER Lithography [4], IMS Nanofabrication [5], Vistec Electron Beam [6], KLA Tencor [7], Multibeam [8] or Advantest [9] is currently being developed but still several years away from full mass manufacturing. Optical lithography using 193nm immersion on the other hand is now moving towards the 28nm mass manufacturing node and beyond by applying costly multiple patterning solutions such as self-aligned or spacer assisted double patterning (SADP) [10] or sophisticated exposure technologies like source-mask optimization (SMO) or inverse lithography. Cost and complexity are exploding as a multitude of mask sets, exposure steps and other single process steps such as CVD, etch and metrology has to be applied.…”

Section: Introductionmentioning

confidence: 99%

Feasibility study of optical/e-beam complementary lithography

Hohle¹,

Choi²,

Freitag³

et al. 2012

Alternative Lithographic Technologies IV

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Using electron beam direct write (EBDW) as a complementary approach together with standard optical lithography at 193nm or EUV wavelength has been proposed only lately and might be a reasonable solution for low volume CMOS manufacturing and special applications as well as design rule restrictions. Here, the high throughput of the optical litho can be combined with the high resolution and the high flexibility of the e-beam by using a mix & match approach (Litho- Etch-Litho-Etch, LELE). Complementary Lithography is mainly driven by special design requirements for unidirectional (1-D gridded) Manhattan type design layouts that enable scaling of advanced logic chips. This requires significant data prep efforts such as layout splitting. In this paper we will show recent results of Complementary Lithography using 193nm immersion generated 50nm lines/space pattern addressing the 32nm logic technology node that were cut with electron beam direct write. Regular lines and space arrays were patterned at GLOBALFOUNDRIES Dresden and have been cut in predefined areas using a VISTEC SB3050DW e-beam direct writer (50KV Variable Shaped Beam) at Fraunhofer Center Nanoelectronic Technologies (CNT), Dresden, as well as on the PML2 tool at IMS Nanofabrication, Vienna. Two types of e-beam resists were used for the cut exposure. Integration issues as well as overlay requirements and performance improvements necessary for this mix & match approach will be discussed

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Sustainability and applicability of spacer-related patterning towards 7nm node

Oyama

Yamauchi

Hara

et al. 2015

Advances in Patterning Materials and Processes XXXII

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Self-aligned multiple patterning technique has enabled the further down scaling through 193 immersion lithography extension [1][2][3][4][5]. In particular, focus on the logic device scaling, we have finished the verification of patterning technology of up to 10nm node [6-7], we will discuss about some patterning technologies that are required to 7nm node. For critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for pattern cutting process. In 7nm node, cutting number increase in metal or fin layer, and also pattern splitting of contact or via is complicated, so both cost reduction and process controllability including EPE are strongly required. For example, inverse hardmask scheme in metal layer can improve CD variation of the Cu wiring. Furthermore hole pattern shrink technology in contact layer, by the combination with the exposure technique which has k1 0.25 or less, can achieve both cost reduction and reducing the numbers of pitch splitting. This paper presents the possibility of immersion-based multiple patterning techniques for up to 7nm node.

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The important challenge to extend spacer DP process towards 22nm and beyond

Cited by 17 publications

References 0 publications

Extendibility of self-aligned type multiple patterning for further scaling

Extendibility of self-aligned type multiple patterning for further scaling

Feasibility study of optical/e-beam complementary lithography

Sustainability and applicability of spacer-related patterning towards 7nm node

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