The integration of proton bombardment process into the manufacturing of mixed-signal/RF chips

Tang, D.D.; Lin, Wei–Chun; Lai, Li-Shyue; Wang, C.H.; Lee, L.P.; Hsu, Humning; Wu, Cheng‐Hsun; Chang, Chi Cheng; Lien, W.Y.; Chao, Calvin Yi‐Ping; Lee, C.Y.; Chern, G.J.; Guo, Jyh–Chyurn; Sun, Yi‐Chiang; Du, Dongdong; Lan, Kai-Wei; Lin, Lu

doi:10.1109/iedm.2003.1269370

Cited by 10 publications

(5 citation statements)

References 2 publications

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“…From the measured results, when the distance is larger than 15 μm, the leakage current of transistors on both sides does not increase, which indicate that the irradiation has no effect on the transistors. Therefore, a distance of at least 15 μm is the required margin for transistors including the mask alignment, while 50 μm is required in the proton bombardment [6] due to the enormous dose and lateral scattering.…”

Section: A Substrate Resistivitymentioning

confidence: 99%

“…loss. For the latter one, the proton bombardment [4]- [6] and the use of postpassivation interconnect (PPI) [7]- [10] have been proposed for realizing high-Q inductors by decrease the substrate loss. However, the PPI inductor cannot be used for high-frequency applications due to the large parasitics of the high aspect ratio vias, which are used to connect PPI inductors and circuits, resulting in a low self-resonance frequency of 16 GHz [7].…”

mentioning

confidence: 99%

“…The bombardment technique can decrease substrate loss by creating locally semi-insulating substrate areas with substrate resistivity [5]. However, the proton bombardment [4]- [6] requires an enormous dose of 10 15 cm −2 to realize a resistivity of more than 10 3 • cm for an originally 15-• cm substrate [5], which results in less reliability and high process cost. Other methods such as silicon on insulator (SOI) technique can also improve the quality factor [11].…”

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confidence: 99%

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High-$Q$ Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits

Okada

Inoue³

et al. 2015

IEEE Trans. Electron Devices

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A helium-3 ion bombardment technique is proposed to realize high-Q inductors by creating locally semi-insulating substrate areas. A dose of 1.0 × 10 13 cm −2 helium-3 increases a Si substrate resistivity from 4• cm to above 1 k • cm, which improves the quality factor of a 2-nH inductor with a 140-μm diameter by 38% ( Q = 16.3). An aluminum mask is used for covering active areas, and at least 15-μm distance from the mask edge is required to avoid the p-n junction leakage. The proposed technique is applied to an 8-GHz oscillator, and an 8.5 dB improvement of the measured phase noise has been achieved.

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Section: A Substrate Resistivitymentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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High-$Q$ Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits

Okada

Inoue³

et al. 2015

IEEE Trans. Electron Devices

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“…This region is the so-called TEM mode or inductor mode, which favors the inductor operation with high Q attributed to suppressed resonance in a substrate of dielectric property. Note that the saturation of f SR under further increasing substrate resistivities beyond the standard Si, i.e., ρ Si > 10 Ω • cm, can be supported by the experimental results reported in the 2003 IEEE International Electron Devices Meeting [8], in which ultrahigh resistivity substrates with ρ Si > 10 4 −10 5 Ω • cm were achieved through proton bombardment, which effectively raised Q by around 100% but retained an almost negligible change in f SR . With regard to the very low resistivity region of ρ Si < 0.5 Ω • cm, f SR saturates at a minimum and Q m drops drastically.…”

Section: Operation Modes Of Varying Substrate Resistivitiessupporting

confidence: 58%

A Broadband and Scalable On-chip Inductor Model Appropriate for Operation Modes of Varying Substrate Resistivities

Guo

Tan

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006

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A broadband and scalable model is developed to accurately simulate on-chip inductors with various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies of up to 20 GHz, even beyond resonance. A new scheme of resistance-inductance-capacitance networks is deployed for the spiral coils and substrate to account for 3-D eddy current, substrate return path, and spiral coil to substrate coupling effects. The 3-D eddy current is identified as the key element essential to accurately simulate the broadband characteristics. Electromagnetic simulation using the Advanced Design System momentum is conducted to predict the on-chip inductor performance corresponding to a wide range of substrate resistivities (ρ Si = 0.05−1 kΩ • cm). Three operation modes such as transverse electromagnetic mode, slow-wave mode, and eddy current mode are reproduced. The model parameters manifest themselves as physics-based through relevant correlation with ρ Si over three operation modes. The onset of slow-wave mode can be consistently explained by a key element R P introduced in our model, which accounts for the conductor loss due to an eddy current arising from magnetic field coupling through a substrate return path. This broadband and scalable model is useful for radio frequency circuit simulation. In addition, it can facilitate an optimum design of on-chip inductors through the physics-based model parameters relevant to varying substrate resistivities.

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“…However, the use of ultra-thick Cu at 6 m combined with ground shielding [5] can further improve Q to peak GHz . The comparison suggests that an ultra-thick coil metal and elaborated ground shielding or semi-insulating substrate [23] will help to improve Q for the on-chip inductors. A differential-type inductor can achieve superior Q even without using ultra-thick metal.…”

Section: ) Rf Passive Device Technology and Performance Benchmarkmentioning

confidence: 96%

Low-K/Cu CMOS-Based SoC Technology With 115-GHz<tex>$f_T$</tex>, 100-GHz<tex>$f_max$</tex>, Low Noise 80-nm RF CMOS, High-Q MiM Capacitor, and Spiral Cu Inductor

Guo

2006

IEEE Trans. Semicond. Manufact.

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Logic CMOS-based RF technology is introduced for a 10-Gb transceiver in which active and passive RF devices have been realized in a single chip. RF nMOS of 115-GHz , 100-GHz max , and sub-1.0-dB NF min at 10 GHz have been fabricated by aggressive device scaling and layout optimization. High-Q MiM capacitor and spiral Cu inductors have been successfully implemented in the same chip by 0.13-m low-K/Cu back end of integration line technology. Core 1.0 V MOS and/or junction varactors for VCO at 10 GHz are offerings free of extra cost and realized by the elaborated layout.

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The integration of proton bombardment process into the manufacturing of mixed-signal/RF chips

Cited by 10 publications

References 2 publications

High-$Q$ Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits

High-$Q$ Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits

A Broadband and Scalable On-chip Inductor Model Appropriate for Operation Modes of Varying Substrate Resistivities

Low-K/Cu CMOS-Based SoC Technology With 115-GHz<tex>$f_T$</tex>, 100-GHz<tex>$f_max$</tex>, Low Noise 80-nm RF CMOS, High-Q MiM Capacitor, and Spiral Cu Inductor

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