The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors

Hsieh, E. R.; Chung, Steve S.

doi:10.1063/1.4768687

Cited by 6 publications

(3 citation statements)

References 21 publications

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“…Besides, it is worth to note that for the devices after HC stress, σI g is proportional to the inverse of the square root of device area. [8] For σI g after the NBTI stress, Fig. 20 shows that σI g increases dramatically after NBTI stress but is recovered a little bit after the recovery time, which is similar to σV th suffered from the NBTI cycles (Fig.…”

Section: B Stress-induced Gate Current Variationsupporting

confidence: 55%

Gate current variation: A new theory and practice on investigating the off-state leakage of trigate MOSFETs and the power dissipation of SRAM

Hsieh

Lin

Chung

et al. 2013

2013 IEEE International Electron Devices Meeting

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A new gate current variation (σI g ) has been proposed for the first time and demonstrated on the trigate devices. It was found that gate current variation can serve as an indicator of the gate sidewall surface roughness. A new theory has then been developed and verified experimentally on trigate devices with various fin heights. Results show that surface roughness increases with the increasing fin height. In addition, hot carrier and NBT stresses have also been performed for trigate CMOS devices. It was found that NBTI exhibits the worst I g variation. Finally, this theory has been tested on the SRAM to examine the standby power dissipation. Results show that the power dissipation is dominated by the pFET NBTI effect.IEDM13-773 31.2.4

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Section: B Stress-induced Gate Current Variationsupporting

confidence: 55%

Gate current variation: A new theory and practice on investigating the off-state leakage of trigate MOSFETs and the power dissipation of SRAM

Hsieh

Lin

Chung

et al. 2013

2013 IEEE International Electron Devices Meeting

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“…Fig. 8 The fin height poses certain constraint to the development of trigate device as a result of the corner effect, especially for the future trigate device manufacturing since the fin height is closely related to the random trap fluctuation [14], corner effect [15], and gate dielectric surface roughness effect etc. In summary, an experimental dopant profiling technique has been demonstrated on very small dimension strained-silicon and trigate devices.…”

Section: Results On the Trigate Cmos Devicesmentioning

confidence: 99%

(Invited) The Random Dopant Fluctuations of Ultra-Scaled CMOS Devices

Chung

2014

ECS Trans.

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This paper demonstrates the methodology to understand the random dopant fluctuation (RDF) from the electrical measurements. The theoretical basis from an experimental discrete dopant profiling technique has first been introduced to analyze the RDF effect. It was further demonstrated on the advanced strain-silicon devices and advanced trigate devices. The discrete dopant distributions along the channel direction can be achieved, followed by the demonstration of the dopant fluctuation in SiC S/D strained and SiGe S/D strained nMOSFETs and pMOSFETs respectively. The carbon or Ge outdiffusion can be easily detected by this method. Finally, experiments have been extended to the advanced bulk-trigate CMOS devices. The sidewall corner effect in trigate has also been studied. It reveals that the corner effect is very challenging for the manufacturing. This approach provides a simple way to monitor the random dopant fluctuation as well as for the quality monitoring of future generation trigate devices.

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“…The impact of interface and oxide traps on MOSFET characteristics is crucial and still of fundamental importance. [1][2][3][4][5][6][7][8][9][10][11][12][13] Stress induced build-up of charged defects can heavily disturb the electrostatics of a MOSFET. During device operation each trap can be charged or discharged and the kinetics of this process is defined by capture and emission times.…”

Section: Introductionmentioning

confidence: 99%

An analytical approach for the determination of the lateral trap position in ultra-scaled MOSFETs

Illarionov

Bina

Tyaginov

2014

Jpn. J. Appl. Phys.

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We propose a new method to determine the lateral trap position in ultra-scaled MOSFETs with a precision of less than 1 nm. The method is based on an analytical model which links the surface potential in the presence of a discrete trap to the drain voltage. We demonstrate that the dependence between the surface potential in the damaged region of the channel and the drain voltage is quasi-linear. The unique slope of this dependence corresponds to a particular lateral trap position and can thus be used as a fingerprint to locate the trap. A high accuracy is reached due to a negligibly small impact of the random dopant fluctuations on the slope magnitude. To verify our analytical approach we employ standard technology computer aided design (TCAD) methods, including random discrete dopants for both n-and p-MOSFETs with various channel lengths.

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The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors

Abstract: Articles you may be interested in Physical understanding of different drain-induced-barrier-lowering variations in high-k/metal gate n-channel metal-oxide-semiconductor-field-effect-transistors induced by charge trapping under normal and reverse channel hot carrier stresses Appl.

Cited by 6 publications

References 21 publications

Gate current variation: A new theory and practice on investigating the off-state leakage of trigate MOSFETs and the power dissipation of SRAM

Gate current variation: A new theory and practice on investigating the off-state leakage of trigate MOSFETs and the power dissipation of SRAM

(Invited) The Random Dopant Fluctuations of Ultra-Scaled CMOS Devices

An analytical approach for the determination of the lateral trap position in ultra-scaled MOSFETs

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