The Molen compiler for reconfigurable processors

Abstract

In this paper, we describe the compiler developed to target the Molen reconfigurable processor and programming paradigm. The compiler automatically generates optimized binary code for C applications, based on pragma annotation of the code executed on the reconfigurable hardware. For the IBM PowerPC 405 processor included in the Virtex II Pro platform FPGA, we implemented code generation, register, and stack frame allocation following the PowerPC EABI (embedded application binary interface). The PowerPC backend has been extended to generate the appropriate instructions for the reconfigurable hardware and data transfer, taking into account the information of the specific hardware implementations and system. Starting with an annotated C application, a complete design flow has been integrated to generate the executable bitstream for the reconfigurable processor. The flexible design of the proposed infrastructure allows to consider the special features of the reconfigurable architectures. In order to hide the reconfiguration latencies, we implemented an instruction-scheduling algorithm for the dynamic hardware configuration instructions. The algorithm schedules, in advance, the hardware configuration instructions, taking into account the conflicts for the reconfigurable hardware resources (FPGA area) between the hardware operations. To verify the Molen compiler, we used the multimedia video frame M-JPEG encoder of which the extended discrete cosine transform (DCT*) function was mapped on the FPGA. We obtained an overall speedup of 2.5 (about 84% efficiency over the maximal theoretical speedup of 2.96). The performance efficiency is achieved using automatically generated nonoptimized DCT* hardware implementation. The instruction-scheduling algorithm has been tested for DCT, quantization, and VLC operations. Based on simulation results, we determine that, while a simple scheduling produces a significant performance decrease, our proposed scheduling contributes for up to 16x M-JPEG encoder speedup.

Self-Aware Adaptation in FPGA-based Systems

“…FPGA-based reconfigurable architecture has been used in cooperation with ad-hoc, or extended version of standard compiler to create runtime adaptable system, as presented in [11,12]. These approaches take advantages by the use of the compiler optimization to create the supposed to be, best configuration for a given application.…”

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

“…However, one of the existing drawbacks of this framework is the lack of available support for a high abstraction level design methodology, in order to reduce design complexity. Additionally, works such as Molen (Panainte et al 2007) propose efficient compilers for reconfigurable architectures. The proposed Molen compiler was implemented on a Virtex II FPGA, and takes into account details such as related to synthesis placement conflicts as well as reconfiguration latencies.…”

General Purpose Computing with Reconfigurable Acceleration

“…Additionally the compiler plug-in must be modified to insert a call to this set instruction before any call to the execute instruction. A simplistic method to achieve this would be to simply insert the set instruction before the execute instruction, but [27] has already shown that better performance can be gained by inserting the call at earlier times. The methods described there can easily be applied to the compiler plug-in, or the other way around.…”