The MU5 Multicomputer Communication System

Lavington, Simon; Thomas, Gareth; Edwards, D. Brent

doi:10.1109/tc.1977.5009269

Cited by 3 publications

(1 citation statement)

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“…Thus the final configuration of the processor is as shown in Figure 4. PROP is supplied with instructions by the instruction buffer unit (IBU), and the virtual to real address translation takes place within the store access control unit (SAC), which coordinates requests to the local store, and is also linked to the exchange, an autonomous packet switching system [9], which links together all the units in the MU5 complex (Section 6). SAC also developed into a pipeline structure, in parallel with the development of the primary and secondary operand units.…”

Section: Design Of the Processormentioning

confidence: 99%

The development of the MU5 computer system

Capon

1978

Commun. ACM

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Following a brief outline of the background of the MUS project, the aims and ideas for MU5 are discussed. A description is then given of the instruction set, which includes a number of features conducive to the production of efficient compiled code from high-level language source programs. The design of the processor is then traced from the initial ideas for an associatively addressed "name store" to the final multistage pipeline structure involving a prediction mechanism for instruction prefetching and a function queue for array element accessing. An overall view of the complete IVIU5 complex is presented together with a brief indication of its performance.

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Section: Design Of the Processormentioning

confidence: 99%