The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets

Feehrer, John; Jairath, Sumti; Loewenstein, Paul; Sivaramakrishnan, Ram; Smentek, David; Turullols, Sebastian; Vahidsafa, Ali

doi:10.1109/mm.2013.49

Cited by 31 publications

(13 citation statements)

References 3 publications

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“…As for L1i, it was set equal to the half size of L1d. In Conventional L1+L2, L2 was set equal to 8 times of L1d, as in Sparc T5 [18]. These along with the related physical layer metrics of optical cache [10] were incorporated in the Gem5 and are listed in Table I For our study, we chose the Timing Simple CPU model.…”

Section: Simulation Resultsmentioning

confidence: 99%

High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures

Maniotis

Gitzenis

Pleros

2015

2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing

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We present an optical bus-based Chip Multiprocessor architecture where the processing cores share an optical single-level cache unit. Physically, the optical cache is implemented externally in a separate chip located next to the CPU die. The cache interconnection system is realized through WDM optical interfaces that connect the shared cache module with the processing cores and the Main Memory via spatialmultiplexed optical waveguides; hence, the CPU-DRAM communication completely takes place in the optical domain. To evaluate the shared optical cache approach, we carry out systemlevel simulations of 6 realistic processor parallel workloads via the Gem5 platform. The optical cache architecture is compared against the conventional electronic Chip Multiprocessor topology that uses dedicated on-chip L1 electronic caches and a shared L2 cache. The results show significant reduction in the L1 miss rate of up to 96% for certain cases; on average, a performance speedup of up to 20.53% or a reduction of up to 65.8% in cache capacity requirements is attained. Combined with highbandwidth CPU-DRAM bus solutions based on optical interconnects, the proposed design is a quite promising system architecture that bridges the gap between high-speed optically connected CPU-DRAM schemes and high-speed optical memory technologies.

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Section: Simulation Resultsmentioning

confidence: 99%

High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures

Maniotis

Gitzenis

Pleros

2015

2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing

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“…This leaves parallelism as the only option to allow fast processing for the growing amounts of memory-resident data. The computer architecture community considered two approaches to leverage parallelism, namely (i) off-the-shelf multi-core architectures, including CPUs and GPUs, [2,10] or (ii) customizable architectures such as CPUs with FPGAs [14,18,13,16,21,20]. While multi-cores typically have much higher clock speeds, specialized hardware (e.g., FPGA) has both the advantages of customization (the hardware design is optimized for a specific application) and parallelism.…”

Section: Introductionmentioning

confidence: 99%

“…The executing thread is then suspended until the long-latency operation completes and eventually returns to a ready state again. This approach has been used in multicores (UltraSparc [10]). However these architectures support a relatively small number of threads because the CPU has to provision a full hardware context for each ready/waiting thread, thereby limiting the amount of parallelism.…”

Section: Introductionmentioning

confidence: 99%

FPGA-accelerated group-by aggregation using synchronizing caches

Absalyamov

Budhkar

Windh

et al. 2016

Proceedings of the 12th International Workshop on Data Management on New Hardware

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Recent trends in hardware have dramatically dropped the price of RAM and shifted focus from systems operating on disk-resident data to in-memory solutions. In this environment high memory access latency, also known as memory wall, becomes the biggest data processing bottleneck. Traditional CPU-based architectures solved this problem by introducing large cache hierarchies. However algorithms which experience poor locality can limit the benefits of caching. In turn, hardware multithreading provides a generic solution that does not rely on algorithm-specific locality properties.In this paper we present an FPGA-accelerated implementation of in-memory group-by hash aggregation. Our design relies on hardware multithreading to efficiently mask long memory access latency by implementing a custom operation datapath on FPGA. We propose using CAMs (Content Addressable Memories) as a mechanism of synchronization and local pre-aggregation. To the best of our knowledge this is the first work, which uses CAMs as a synchronizing cache. We evaluate aggregation throughput against the state-of-the-art multithreaded software implementations and demonstrate that the FPGA-accelerated approach significantly outperforms them on large grouping key cardinalities and yields speedup up to 10x.

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“…To sustain performance advances towards Exascale, modern HPC systems rely on increasing the density of compute nodes and integrating multicore chips [1], putting more pressure on the system interconnect within HPCs. To overcome this drawback electrical interconnects are already being replaced by Active Optical Cables (AOCs) in rack-to-rack communication, while midboard optical subassemblies and compact board-level flexible modules (FlexPlane) [2] have already entered the market.…”

Section: Introductionmentioning

confidence: 99%