The Paradigm compiler for distributed-memory multicomputers

Banerjee, P.; Chandy, John A.; Gupta, Manish; Hodges, Iv. E.W.; Holm, John G.; Lain, Antonio; Palermo, Daniel J.; Ramaswamy, S.; Su, Ernesto

doi:10.1109/2.467577

Cited by 148 publications

(70 citation statements)

References 10 publications

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“…This is mainly due to: (1) inter- 6 We compute the energy consumption as follows: 30% of the available memory slots are used; (2) we do not use power hungry multi-port memories. Consequently, we cannot schedule operations that access the same data in parallel.…”

Section: Access Conflicts Reduce the System's Performancementioning

confidence: 99%

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Power-efficient data management for dynamic applications

Marchal

Perez

Atienza

et al. 2006

System-on-Chip: Next Generation Electronics

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multi-processor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility also perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads running on the different processors into account, only locally optimize the bandwidth nor deal with the dynamic behavior of these applications. The contributions of this chapter are to outline the main limitations of current techniques and to introduce an approach for dealing with the dynamic multi-threaded of our application domain. The design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [53]. These systems require an enormous computational performance (40GOPS 1 ). Even though current PCs offer this performance requirement, they consume too much power (10-100W). Mobile devices should consume at least two or three orders of magnitude less power [30]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. The era of platform-based designA platform is a fixed micro-architecture together with a programming environment that minimizes mask-making costs and is flexible enough to work for a set of applications [4]. The production volumes can then remain high over an extended chip lifetime.Given the strong energy constraints, we must choose the flavor of these platforms. Since power is cubic to the processing frequency, parallelism is an effective to reduce power and energy consumption. Then, multiple simple processors are preferred to one complex speculative and out-of-order processor. In the right application domain, we can get better performance and spend less energy. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a Digital Signal Processor (DSP). The RISC is more energy-efficient for the input/output processing and simple control-dominated 1 Giga Operations Per Second

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Section: Access Conflicts Reduce the System's Performancementioning

confidence: 99%

“…A large body of research exists in the high-performance computing domain on parallelizing applications while reducing the communication cost (e.g., the SUIF-project [19] and the Paradigm compiler [6]). However, they target an architecture which is very different from ours.…”

Section: Memory Optimization In Multi-threaded Applicationsmentioning

confidence: 99%

Power-efficient data management for dynamic applications

Marchal

Perez

Atienza

et al. 2006

System-on-Chip: Next Generation Electronics

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“…Current compiler technology [7][8][9][10][11] can efficiently automate the introduction of OpenMP directives to regular loops that iterate over random-access arrays as defined by Fortran or C. However, because most C++ programs, including many scientific applications, use higher-level abstractions for which semantics are unknown to the compiler, these abstractions are left unoptimized by most parallelizing compilers. By providing mechanisms to optimize object-oriented library abstractions, we thus allow the efficient tailoring of the programming environment as essentially a programming language that is more domain-specific than a general purpose language could allow, thereby allowing the improvement of programmer productivity without degrading application performance.…”

Section: Parallelizing User-defined Containers Using Openmpmentioning

confidence: 99%

Semantic-Driven Parallelization of Loops Operating on User-Defined Containers

Quinlan

Schordan

et al. 2004

Languages and Compilers for Parallel Computing

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Abstract. We describe ROSE, a C++ infrastructure for source-to-source translation, that provides an interface for programmers to easily write their own translators for optimizing user-defined high-level abstractions. Utilizing the semantics of these high-level abstractions, we demonstrate the automatic parallelization of loops that iterate over user-defined containers that have interfaces similar to the lists, vectors and sets in the Standard Template Library (STL). The parallelization is realized in two phases. First, we insert OpenMP directives into a serial program, driven by the recognition of the high-level abstractions, containers, that are thread-safe. Then, we translate the OpenMP directives into library routines that explicitly create and manage parallelism. By providing an interface for the programmer to classify the semantics of their abstractions, we are able to automatically parallelize operations on containers, such as linked-lists, without resorting to complex loop dependence analysis techniques. Our approach is consistent with general goals within telescoping languages.

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“…the SUIF project [40 -42] and the Paradign compiler [43,44]). However, they target an architecture which is very different from ours.…”

Section: Memory Optimisation In Multi-threaded Applicationsmentioning

confidence: 99%

Power aware data and memory management for dynamic applications

Marchal

Perez

Atienza

et al. 2005

IEE Proc., Comput. Digit. Tech.

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multiprocessor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads into account and do not deal with the dynamic behaviour of these novel applications. The main limitations of current techniques are outlined and an approach for dealing with them is introduced. Design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [1]. These systems require an enormous computational performance: 40 gigaoperations per second (GOPS). Even though current PCs could provide sufficient performance, they are too powerhungry (10 -100 W). Mobile devices should consume at least two or three orders of magnitude less [2]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently, and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. Era of platform-based designA platform is a fixed microarchitecture together with a programming environment that minimises mask-making costs and is flexible enough to work for a set of applications [3]. The production volumes can then remain high over an extended chip lifetime.To cope with the energy constraints, platforms usually consist of multiple processors. Since power is cubic to the processing frequency, parallelism is an effective way to reduce it. Therefore, on most platforms two or more processors are integrated. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a digital signal processor (DSP). The RISC is more energy-efficient for the input=output processing and control-dominated applications. The DSP, however, provides the computational performance for audio and video processing, while keeping the energy cost bounded. Indeed, taking a look to the current market offers (e.g. ST Nomadik

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The Paradigm compiler for distributed-memory multicomputers

Cited by 148 publications

References 10 publications

Power-efficient data management for dynamic applications

Power-efficient data management for dynamic applications

Semantic-Driven Parallelization of Loops Operating on User-Defined Containers

Power aware data and memory management for dynamic applications

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