The past present and future of design-technology co-optimization

Yeric, Greg; Cline, Brian; Sinha, Saurabh; Pietromonaco, David; Chandra, Vikas; Aitken, Rob

doi:10.1109/cicc.2013.6658476

Cited by 31 publications

(8 citation statements)

References 18 publications

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“…The communication was primarily unidirectional, from fab to designer in the form of increasingly restrictive design rule checks (DRC) 3 . DFM is the DRC check prior to the tape-out.…”

Section: Dtco Vs Dfmmentioning

confidence: 99%

Design technology co-optimization for 14/10nm metal1 double patterning layer

Duan¹,

Su²,

Chen³

et al. 2016

SPIE Proceedings

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Design and technology co-optimization (DTCO) can satisfy the needs of the design, generate robust design rule, and avoid unfriendly patterns at the early stage of design to ensure a high level of manufacturability of the product by the technical capability of the present process. The DTCO methodology in this paper includes design rule translation, layout analysis, model validation, hotspots classification and design rule optimization mainly. The correlation of the DTCO and double patterning (DPT) can optimize the related design rule and generate friendlier layout which meets the requirement of the 14/10nm technology node. The experiment demonstrates the methodology of DPT-compliant DTCO which is applied to a metal1 layer from the 14/10nm node. The DTCO workflow proposed in our job is an efficient solution for optimizing the design rules for 14/10 nm tech node Metal1 layer. And the paper also discussed and did the verification about how to tune the design rule of the U-shape and L-shape structures in a DPT-aware metal layer.

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“…The communication was primarily unidirectional, from fab to designer in the form of increasingly restrictive design rule checks (DRC) 3 . DFM is the DRC check prior to the tape-out.…”

Section: Dtco Vs Dfmmentioning

confidence: 99%

Design technology co-optimization for 14/10nm metal1 double patterning layer

Duan¹,

Su²,

Chen³

et al. 2016

SPIE Proceedings

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“…Other changes, such as the more extensive use of local interconnects, provides new opportunities for design optimization. Both the challenges and opportunities require a better vertically integrated flow that provides early feedback and involvement of design and EDA [10,11]. We need to fundamentally change the existing flow, which is design/EDA work with an already defined technology and find solutions in the late stage of overall technology development, to a more open and effective design-technology-manufacturing co-optimization flow, where the design/EDA input can be considered during the early phase of technology definition (Figure 9).…”

Section: Future Challenges and Oppotunitiesmentioning

confidence: 99%

Technology-design-manufacturing co-optimization for advanced mobile SoCs

et al. 2014

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How to maintain the Moore's Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

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“…This section follows the general flow of [1, 2]. In past technology nodes, foundries’ continued ability to deliver process node scaling meant that the rest of the ecosystem (fabless IC companies, along with IP, EDA, packaging, test and assembly etc.)…”

Section: History Of Co‐optimisationmentioning

confidence: 99%

Predicting future complementary metal–oxide–semiconductor technology – challenges and approaches

Aitken

Chandra

Cline

et al. 2016

IET Computers & Digital Techniques

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Long timescales and complex design processes require that CPU architects and microarchitects have early access to information about future manufacturing processes. In some cases, this means that future technology must be predicted in advance of it actually being developed. In addition, close collaboration with the foundries, known as 'Design-Technology Co-Optimisation', or DTCO, allows the mutual influence during development of microarchitecture, physical IP (standard cells and memories), and process technology. This predictive technology, in conjunction with early technology information or not, allow design exploration in the form of trial runs of synthesis, place and route to determine the predicted effects of various technology choices on CPU power, performance, and area. 2.1 Restrictive design rules Note that in the following discussion, process nodes are used somewhat generically. There were and are significant differences IET Computers & Digital Techniques Special Issue: Current and Future Trends in Computer Engineering and Digital Techniques

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The past present and future of design-technology co-optimization

Cited by 31 publications

References 18 publications

Design technology co-optimization for 14/10nm metal1 double patterning layer

Design technology co-optimization for 14/10nm metal1 double patterning layer

Technology-design-manufacturing co-optimization for advanced mobile SoCs

Predicting future complementary metal–oxide–semiconductor technology – challenges and approaches

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