The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor

Slaton, J.; Licht, S.P.; Alexander, M.; Reeves, Scott; Jessani, R.; Kishore, K.R.

doi:10.1109/iccd.1995.528810

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…In recent years, a nu mber of researches have been proposed for Implementation of microprocessor by using the FPGA by some co mpanies [4][5][6][7][8][9][10][11]. In continuing we present some researches, The Aviation Microelectronic Center of NPU (Northwestern Polytechnical University) has recently comp leted the development of a 32-bit super-scalar RISC microprocessor, called " Longtium" R2.…”

Section: Introductionmentioning

confidence: 99%

“…In [4], the arch itecture of " Longtium" R2 is presented. As exp lained in [5], the PowerPC 603e microprocessor is a high performance, low cost, low power microprocessor designed for use in portable computers. The 603e is an enhanced version of the PowerPC 603 microprocessor and extends the performance range of the PowerPC microprocessor family of portable products.…”

Section: Introductionmentioning

confidence: 99%

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Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA

Daghooghi

2013

IJMECS

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This paper presents the design and development of a high performance and low power MIPS microprocessor and implementation on FPGA. In this method we for achieving high performance and low power in the operation of the proposed microprocessor use different methods including, unfolding transformation (parallel processing), C-slow retiming technique, and double edge registers are used to get even reduce power consumption. Also others blocks designed based on high speed digital circuits. Because of feedback loop in the proposed architecture C-slow retiming can enhance designs that contain feedback loops. The C-slow retiming is well-known for optimization and high performance technique, it automatically rebalances the registers in the proposed design. The proposed high performance microprocessor is modeled and verified using FPGA and simulation results. The proposed methods in microprocessor have been successfully synthesized and implemented in Quartus II 9.1 and Stratix II FPGA, to target device EP2S15F484C3, and power is analyzed with Xpower analyzer. Results demonstrate that the proposed method has high performance

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA

Daghooghi

2013

IJMECS

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A G3 PowerPC/sup TM/ superscalar low-power microprocessor

Kennedy

Alexander

Fiene

et al.

Proceedings IEEE COMPCON 97. Digest of Papers

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This microprocessor is a the third generation PowerPC microprocessor and is a member of the G3 family of PowerPC processor products. Although it's high performance (estimated 10.0 SPECint95) makes it suited for high end desktop systems, it's low typical power dissipation of 5W and size of 66.5mm2 make it very attractive for portable systems as well. This microprocessor is a dual-issue superscaler machine with a four stage pipeline, separate Instruction and Data side L l caches (32KB each), and full tags and support for up to a IMB of back-side L2. A Thermal Assist Unit and I-cache Throttling feature are included in the microprocessor as additional tools for thermal management. This microprocessor was designed in a 0.25um CMOS process (0.1 8um Leff) to operate at a frequency of 250MHz.

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A 200 MHz 2.5 V 4 W superscalar RISC microprocessor

Sanchez

Eisen²,

Croxton³

et al.

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

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This RISC microprocessor is based on a microarchitecture designed in a 2.5V CMOS technology [l]. The 78.75mm2 design features dual 16kB instruction and data caches, a floating-point unit, an integer unit, a branch unit, a loadstore unit, and a system unit. Two instructions per cycle can be dispatched in this superscalar design. The user-configurable multiplying PLL provides a processor clock at 2X, 2.5X, 3X, 3.5X, 4X, 4.5X, 5X, 5.5X, and 6X the bus clock frequency. Testability features include level-sensitive-scan-design (LSSD), array-built-in-self-test (ABIST) logic for cache and tag arrays, and a JTAG interface [21. Figure 1 is a block diagram of the processor, and Figure 2, a micrograph.

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The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor

Cited by 3 publications

References 4 publications

Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA

Design and Development MIPS Processor Based on a High Performance and Low Power Architecture on FPGA

A G3 PowerPC/sup TM/ superscalar low-power microprocessor

A 200 MHz 2.5 V 4 W superscalar RISC microprocessor

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