The PowerPC 603 microprocessor is designed for low powel; low cost computing applications. A RAM builtin-self-test (BIST) implementation tests the split 8k instruction and data caches and the tag arrays, The design is constrained by the need to minimize area overhead while providing high test coverage and rapid atspeed testing. The solution encompasses a novel state machine design built using logic synthesis tools. This paper presents the RAM BIST design implemented on the PowerPC 603 microprocessol:

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IntroductionAs personal digital assistants (PDA's) move into the next generation, there is an obvious need for additional processing power to enable new applications and improve existing ones. While enhanced functionality such as improved handwriting recognition, voice recognition, and speech synthesis are desirable, the size and weight limitations of PDA's require that microprocessors deliver this performance without consuming additional power. The microprocessor described in this paper-the Digital Equipment Corporation SA-110, the first microprocessor in the StrongARM family-directly addresses this need by delivering 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. This represents a significantly higher performance than is currently available at this power level. CMOS Process TechnologyThe chip is fabricated in a 0.35 m three-metal CMOS process with 0.35 V thresholds and 0.25 µm effective channel lengths. Process characteristics are shown in Table 1. The process is the result of several generations of development efforts directed toward highperformance microprocessors. It is identical to the one used in Digital Equipment Corporation's current generation of Alpha chips 2 except for the removal of the fourth layer of metal and the addition of a final nitride passivation required for plastic packaging.The factors which drive process development for low-power design are similar to those which drive the process for pure high-performance although the motivation sometimes differs. For example, while both types of designs benefit from maximizing Idsat of the transistors at the lowest acceptable Vdd, the motivation for a pure high-performance design is reducing power distribution and thermal problems rather than extending battery life. Similar arguments apply to minimizing transistor leakage and on-chip variation of transistor parameters. This convergence of goals has been essential to our ability to develop one process to satisfy the requirements of both low-power and high-performance families.

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