The role of nickel and titanium in the formation of ohmic contacts on p-type 4H–SiC

Laariedh, Farah; Lazar, Mihai; Cremillieu, Pierre; Penuelas, Jose; Leclercq, Jean Louis; Planson, Dominique

doi:10.1088/0268-1242/28/4/045007

Cited by 34 publications

(12 citation statements)

References 21 publications

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“…For that, a classical Ni‐based ohmic contact, RTA annealed at 900 °C, has been implemented on the back side of the n‐type substrate. Then, a Ni/Ti/Al metallic contact was deposited on the top of the VLS p‐type layer by e‐beam evaporation (∼300 nm total thickness), and patterned. No annealing of front side contact has been performed, as it has been demonstrated previously that ohmic contacts can be obtained without any annealing, due to the very high Al doping .…”

Section: Resultsmentioning

confidence: 99%

Further optimization of VLS localized epitaxy for deeper 4H-SiC p-n junctions

Sejil

Lazar

Carole

et al. 2017

Phys. Status Solidi A

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This paper deals with localized epitaxy of highly p-doped 4H-SiC, based on VLS transport, and intended to be used both for the emitter of PN or PiN devices, and for the peripheral protection of power devices. The goal was to fill-in 1 mm-deep wells, plasma etched, into n-type epilayers. We have previously shown that true p-n junctions with low leakage currents can be achieved using this alternative technique without any post-growth annealing at high temperatures. We report here for the first time, the filling of etched wells up to 900 nm with p þþ SiC, presenting a regular and uniform surface morphology. In this work, we also present correlations between the physical analyses of our SiC VLS epitaxy, and the electrical characterizations performed on p/n diodes with VLS grown, locally p-type doped emitter.

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Section: Resultsmentioning

confidence: 99%

Further optimization of VLS localized epitaxy for deeper 4H-SiC p-n junctions

Sejil

Lazar

Carole

et al. 2017

Phys. Status Solidi A

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“…[6]. Ohmic contacts have been obtained using Ni for the back-side of the n + substrate and on n + wells, and using a specific Ni-Ti-Al alloy on the p + wells [7]. These contacts have been annealed by Rapid-Thermal-Annealing under Ar at 900°C and 800°C, respectively.…”

Section: Methodsmentioning

confidence: 99%

The channeling effect of Al and N ion implantation in 4H–SiC during JFET integrated device processing

Lazar

Laariedh

Cremillieu

et al. 2015

Nuclear Instruments and Methods in Physics Research Section B:

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a b s t r a c tA strong channeling effect is observed for the ions of Al and N implanted in 4H-SiC due to its crystalline structure. This effect causes difficulties in subsequent accurate estimation of the depth of junctions formed by multiple ion implantation steps. A variety of lateral JFET transistors integrated on the same 4H-SiC wafer have been fabricated. Secondary Ion Mass Spectrometry measurements and Monte-Carlo simulations were performed in order to quantify and control the channeling effect of the implanted ions. A technological process was established enabling to obtain devices working with the presence of the channeling effect.

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“…Ohmic contacts have been evaluated on these P-type VLS layers with patterned Transfer Length Method (TLM) structures using a specific Ni-Ti-Al metal alloy [15]. The contact is already ohmic without post-metallization annealing.…”

Section: Vapor-liquid-solid Growthmentioning

confidence: 99%

Classic and alternative methods of p-type doping 4H-SiC for integrated lateral devices

Lazar¹,

Carole²,

Raynaud³

et al. 2015

2015 International Semiconductor Conference (CAS)

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P-type 4H-SiC layers formed by ion implantation need high temperature process generating surface roughness, losing and incomplete activation of dopants. Due to dopant redistribution and channeling effect, it is difficult to predict the depth of the formed junctions. Vapor-Liquid-Solid (VLS) selective epitaxy is an alternative method to obtain locally highly doped p-type layers in the 10 20 cm-3 range or more. The depth of this ptype layers or regions is accurately controlled by the initial Reactive-Ion-Etching (RIE) of the SiC. Lateral Junction Field Effect Transistor (JFET) devices are fabricated integrating p-type layers created by Al ion implantation or VLS growth. The P-type VLS layers improve the access resistances on the electrodes of the fabricated devices.

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The role of nickel and titanium in the formation of ohmic contacts on p-type 4H–SiC

Cited by 34 publications

References 21 publications

Further optimization of VLS localized epitaxy for deeper 4H-SiC p-n junctions

Further optimization of VLS localized epitaxy for deeper 4H-SiC p-n junctions

The channeling effect of Al and N ion implantation in 4H–SiC during JFET integrated device processing

Classic and alternative methods of p-type doping 4H-SiC for integrated lateral devices

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