The state-of-the-art of silicon-on-sapphire CMOS RF switches

Thin fim barium strontium titanate capacitors for tunable RF frond-end applications

“…All data are given at 2 GHz unless stated otherwise. The best data found in literature for GaAs pHEMT (0.5 µm) [51] and CMOS(0.18 µm SOI) switch [55] are shown with dash-dotted lines. The solid line is a fit to the best reported measurements of ferroelectric varactors (BaxSr1−xTiO3) at 1 MHz.…”

“…We assume R on ≫ R e . The Q(η) trade-off for CMOS and pHEMT switches becomes [51], and 2. pHEMT switches, on 0.5 µm GaAs at 2 GHz [51], and on 0.15 µm and 0.5 µm GaAs at 0.9 GHz [52] in Figures 2.6 and 2.7, respectively. The best figures of merit R on C off are reported for the case of a 0.5 µm CMOS-switch on Sapphire R on C off,CMOS = 750 fs [51] and a 0.5 µm pHEMT switch R on C off,pHEMT = 360 fs [56].…”

“…The Q(η) trade-off for CMOS and pHEMT switches becomes [51], and 2. pHEMT switches, on 0.5 µm GaAs at 2 GHz [51], and on 0.15 µm and 0.5 µm GaAs at 0.9 GHz [52] in Figures 2.6 and 2.7, respectively. The best figures of merit R on C off are reported for the case of a 0.5 µm CMOS-switch on Sapphire R on C off,CMOS = 750 fs [51] and a 0.5 µm pHEMT switch R on C off,pHEMT = 360 fs [56]. .6 -The performance of CMOS switches in terms of Q and η at 0.7 GHz (0.13 µm Si, RonC off = 56841 fs [53]), 2 GHz (0.18 µm SOI, RonC off = 600 fs [55] and 0.5 µm SOS, RonC off = 756 fs [51]) or 2.4 GHz (0.18 µm Si, RonC off = 13650 fs (series arm) and 29250 fs (shunt arm) [54]) based on a literature survey.…”

“…The best figures of merit R on C off are reported for the case of a 0.5 µm CMOS-switch on Sapphire R on C off,CMOS = 750 fs [51] and a 0.5 µm pHEMT switch R on C off,pHEMT = 360 fs [56]. .6 -The performance of CMOS switches in terms of Q and η at 0.7 GHz (0.13 µm Si, RonC off = 56841 fs [53]), 2 GHz (0.18 µm SOI, RonC off = 600 fs [55] and 0.5 µm SOS, RonC off = 756 fs [51]) or 2.4 GHz (0.18 µm Si, RonC off = 13650 fs (series arm) and 29250 fs (shunt arm) [54]) based on a literature survey. The experimental data from literature are for Si, silicon-on-insulator (SOI) or siliconon-sapphire (SOS) substrates.…”

“…Figure 2.5 -In (a) a schematic picture of a transistor in series with a capacitor is given. If sufficient gate bias Vgate is applied on the transistor, a channel is formed between the source and drain, and the capacitor is connected to the circuit [51]. In (b) the loss-model of the transistor-switched capacitor is depicted [51,52].…”