The Temperature Dependence of Mismatch in Deep-Submicrometer Bulk MOSFETs

Andricciola, Pietro; Tuinhout, H.P.

doi:10.1109/led.2009.2020524

Cited by 52 publications

(22 citation statements)

References 8 publications

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“…For all variants including the reference, the standard deviations of both V t mismatch (figure 10) and relative E mismatch (figure 11) reduce at elevated temperature. This is in line with results found for 65 nm devices [5]. …”

Section: Results At Elevated Temperaturesupporting

confidence: 93%

Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

Wils

Tuinhout

Meijer

2010

2010 International Conference on Microelectronic Test Structures (ICMTS)

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This paper summarizes a comprehensive study on the effect of asymmetrical metal coverage on matching performance for a 45 nm copper damascene based CMOS process. We demonstrate that random mismatch fluctuations are not affected by metal layout asymmetries and we provide valuable new insights about the magnitude of systematic mismatches that can be expected due to asymmetrical layouts and CMP tiling. For the first time we also present results on the impact of temperature increases on both systematic as well as random drain current mismatches.

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Section: Results At Elevated Temperaturesupporting

confidence: 93%

Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

Wils

Tuinhout

Meijer

2010

2010 International Conference on Microelectronic Test Structures (ICMTS)

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“…The drain current mismatch as a function of gate source voltage is shown in Figure 4. As observed in [1], the drain current mismatch decreases with increasing V GS and is largely invariant across temperature at V GS = V DD . This suggests a dopant number fluctuation induced mismatch [4].…”

supporting

confidence: 59%

“…Recent efforts at understanding the effects of temperature on matching [1,2] report improved matching at higher temperatures. Here, we examine the impact of cryogenic temperatures on the matching performance of a 90 nm bulk CMOS technology.…”

mentioning

confidence: 99%

“…Cryogenic operation improves many of the MOSFET performance metrics and cryogenic MOSFETs have been shown to achieve lower broadband noise at cryogenic temperatures [3], opening up the possibility of their application in radio astronomy that require very low noise. As suggested in [1], however, device matching could potentially degrade with cooling. In addition to the enhancement of columbic scattering and the associated variations due to dopant fluctuations [2], cryogenic temperatures impose additional variability due to incomplete ionization and enhanced quantum effects.…”

mentioning

confidence: 99%

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Cryogenic matching performance of 90 nm MOSFETs

Appaswamy

Chakraborty

Cressler

2009

2009 International Semiconductor Device Research Symposium

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While the matching properties of MOSFETs have been extensively studied, the impact of temperature on matching remains poorly understood. Recent efforts at understanding the effects of temperature on matching [1,2] report improved matching at higher temperatures. Here, we examine the impact of cryogenic temperatures on the matching performance of a 90 nm bulk CMOS technology. Cryogenic operation improves many of the MOSFET performance metrics and cryogenic MOSFETs have been shown to achieve lower broadband noise at cryogenic temperatures [3], opening up the possibility of their application in radio astronomy that require very low noise. As suggested in [1], however, device matching could potentially degrade with cooling. In addition to the enhancement of columbic scattering and the associated variations due to dopant fluctuations [2], cryogenic temperatures impose additional variability due to incomplete ionization and enhanced quantum effects.In this work, nMOSFETs of multiple dimensions were layed-out in a common source/body configuration with separate drain and gate contacts. To conserve space, four devices of identical dimensions were placed at minimum distance from each other, constituting six identical device pairs (Figure 1). The devices to be measured were selected by the gate and drain biases. Linear transfer characteristics were measured at a drain-to-source voltage (V DS ) of 50 mV at a body bias of 0 V and -0.6 V. Threshold voltages were extracted using the constant current method at multiple fixed drain currents. A set of 30 device pairs was measured to ensure adequate statistics.The normalized peak transconductance (g m ) of discrete nMOSFETs of multiple device dimensions from the same technology node, as a function of temperature, is shown in Figure 2. As expected, the peak transconductance improves with cooling due to the improvement in mobility. In addition, MOSFETs with larger gate length show a larger improvement in peak g m due to their lower channel doping. The mismatch in threshold voltage (V T ) for three fixed drain currents (I D ) is shown in Figure 3. The V T mismatch decreases with increasing device dimensions (as expected) and increases with cooling (not as expected). Interestingly, the temperature sensitivity of the mismatch is a function of the drain current at which V T is extracted, and the temperature sensitivity decreases with increasing drain currents. In addition, the mismatch worsens with increasing substrate bias.Since current mismatch is a more relevant metric for many circuit applications, we have also included the V T mismatch for constant I D mismatch across temperature in Figure 3. For the same drain current ratio in subthreshold, the threshold voltage mismatch can be expressed as (assuming identical body factor across temperature):(1) Under strong inversion, for the same drain current mismatch, the required threshold voltage mismatch can be expressed as:(2)The more stringent requirement for threshold voltage matching with cooling is due to the improved subthreshold swing...

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“…Then, a first characterization of an improvement with higher temperature of threshold voltage and drain current mismatch was done by Tan et al for 0.18-µm CMOS almost two decades later [94]. More recently, a few characterization studies on modern technology nodes (e.g., 65 nm and 45 nm) have been presented showing again reduction of the mismatch of some parameters at higher temperature [95,96,97]. Finally, also some simulation studies were presented on the thermal energy influence on weak inversion current variation in bulk CMOS [98] and temperature-dependent mismatch even in 16-nm SOI FinFETs [32].…”

Section: Introductionmentioning

confidence: 99%

Interpretation of MOS transistor mismatch signature through statistical device simulations

Andricciola¹

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The Temperature Dependence of Mismatch in Deep-Submicrometer Bulk MOSFETs

Cited by 52 publications

References 8 publications

Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

Influence of metal coverage on transistor mismatch and variability in copper damascene based CMOS technologies

Cryogenic matching performance of 90 nm MOSFETs

Interpretation of MOS transistor mismatch signature through statistical device simulations

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