Thinned wafer multi-stack 3DI technology

Ohba, Takayuki; Maeda, Noritoshi; Kitada, Hideki; Fujimoto, Koji; Suzuki, Kenkichi; Nakamura, Tomoji; Kawai, Akihito; Arai, K.

doi:10.1016/j.mee.2009.07.006

Cited by 88 publications

(35 citation statements)

References 4 publications

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“…The process used for a 90 µm thick SU8 layer deposit is the following: Depositing a seed layer is the next step after dielectric patterning. For this process and like Through Silicon Vias (TSV) technologies [7]- [10], the main challenge for successful 3D electroplating is a void free 3D seed layer. This challenge is affected mainly by the geometry of the sidewalls (vertical, diagonal…), the shape of the dielectric (hollow, pillar) and its thickness, the size of the hollows (if present) and the used equipment (evaporation, sputtering).…”

Section: D Multi-level Interconnect Processmentioning

confidence: 99%

Low cost 3D multilevel interconnect integration for RF and microwave applications

Ghannam

Bourrier

Ourak

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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This work presents a new and low cost multi-level 3D copper interconnect process for RF and microwave applications. This process extends 3D interconnect integration technologies from silicon to above-IC polymer. Therefore, 3D passive devices and multi-level interconnects can be integrated using a single electroplating step making the process suitable for 3D-MMIC integration. 3D interconnects are realized by patterning the SU-8 to specific locations to create the desired 3D shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized electroplating process is later used to grow copper in a 3D technique, insuring transition between all metallic layers. Finally, high-Q (60 @ 6 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process. IntroductionToday, RF and microwave applications demands for increased functionality, higher density integration, better passive device performance, reduced footprint and cost are stressing for new and enhanced integration technologies. To meet these requirements, technologies like 3D-MMIC were introduced [1]- [4]. These technologies look promising because they offer a solution for both miniaturization and passive device performance issues. However, their complexity, cost and processing time increase quickly with each addition of a dielectric or a metallic layer, which hindered their large scale usage. Moreover, the performance of the passive devices is severely limited by the relatively thin dielectric layers. Thus, stacking several dielectric layers is required to improve the performance of these devices which often induces more complications like increased residual stress on the chip and the frequent need for mechanical dielectric leveling steps.In another hand, to overcome 3D-MMIC limitations, a specific 3D interconnect technology is needed to replace current planar technologies used for implementation of passive circuits such as filters, matching networks, transformers ... or for the integration of inductors often realized from bond wires. This implies that the technology must allow the integration of both the interconnect and the vias for underneath connection.Finally, current 3D interconnect technologies are focused on the 3D stacking of integrated circuits, at the IC-fab, or, at package level, to achieve a higher integration density and a smaller footprint of electronic components [5]. Such a technology would be more attractive if it could be applied as well for above-IC passive devices integration. However, this

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Section: D Multi-level Interconnect Processmentioning

confidence: 99%

Low cost 3D multilevel interconnect integration for RF and microwave applications

Ghannam

Bourrier

Ourak

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

View full text Add to dashboard Cite

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“…among the commonly-used bonding adhesives like SU-8 (Iliescu et al 2006), polyimide (Bayrashev andZiaie 2003), and photoresist (Su et al 2001), benzocyclobutene (BcB) has emerging as a widely-used bonding adhesive in the applications of three-dimensional (3-D) integration (Kwon et al 2008;Zhang et al 2006;Kim et al 2013;Ohba et al 2010;lu et al 2003) and MeMS/microsensors (Dragoi et al 2008;Seok et al 2012;Zhou et al 2009;McMahon et al 2008). In MeMS/microsensor applications, BcB has been used as a permanent or temporary bonding material for wafer transfer or heterogeneous integration of MeMS/microsensors and integrated circuits (Brault et al 2010;lapisa et al 2011).…”

Section: Introductionmentioning

confidence: 99%

Void-free BCB adhesive wafer bonding with high alignment accuracy

et al. 2014

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“…Bumpless interconnects using TSVs are a second-generation alternative to the use of TSVs with micro-bumps [7,8,9]. Our bumpless interconnects process involves a Thinning-First process before bonding wafers, followed by a Via-Last process, meaning that interconnects are formed after bonding the wafers, as shown in Figs.…”

Section: Wafer-level 3d Integration Processmentioning

confidence: 99%

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

Ohba

Kim

Mizushima

et al. 2015

IEICE Electron. Express

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The prospects of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of microbumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4 µm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of ThroughSilicon-Vias (TSVs). Our bumpless interconnects technology is classified into Via-Last, which is performed from the front side after thinning, and stacking Back-to-Front, in which any number of thinned 300 mm wafers and/or heterogeneous dies can be integrated. From an economic point of view, in many situations WOW is the leading 3D process because stacking at the wafer level drastically increases the processing throughput, and using multi-level bumpless interconnects, with individual wiring die-to-die, provides an appropriate yield that is equivalent to or greater than that achievable with 2D processes when scaling down to 22 nm nodes and beyond.

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Thinned wafer multi-stack 3DI technology

Cited by 88 publications

References 4 publications

Low cost 3D multilevel interconnect integration for RF and microwave applications

Low cost 3D multilevel interconnect integration for RF and microwave applications

Void-free BCB adhesive wafer bonding with high alignment accuracy

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

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