Three bits per cell floating gate NAND flash memory technology for 30nm and beyond

Nitta, H.; Kamigaichi, T.; Arai, F.; Futatsuyama, T.; Endo, Masamori; Nishihara, N.; Murata, Takahiro; Takekida, H.; Izumi, T.; Uchida, Ken; Maruyama, Toru; Kawabata, I.; Suyama, Y.; Sato, Akira; Ueno, Katsunori; Takeshita, Hiroaki; Joko, Y.; Watanabe, Susumu; Liu, Y.; Meguro, H.; Kajita, Akihiro; Ozawa, Yoshio; Takeuchi, Yoshinori; Hara, T.; Watanabe, T.; Sato, S.; Tomiie, H.; Kanemaru, Y.; Shoji, R.; Lai, Chun‐Hung; Nakamichi, M.; Owada, K.; Ishigaki, Takashi; Hemink, G.; Dutta, Debasree; Yan, Dong; Chen, C.; Liang, Guanfeng; Higashitani, M.; Lutze, J.

doi:10.1109/irps.2009.5173269

Cited by 8 publications

(2 citation statements)

References 4 publications

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“…Besides technology scaling, multilevel per cell (MLC) technique has been widely used to further improve the NAND flash memory storage density. In current design practice, a majority of MLC NAND Flash memories store 2 bits per cell, but recent developments have allowed for 3 and 4 bits per cell [Trinh et al 2009;Li et al 2009;Nitta et al 2009]. …”

Section: Introductionmentioning

confidence: 99%

Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes

Xie

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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This article presents a cross-layer codesign approach to reduce SSD read response latency. The key is to cohesively exploit the NAND flash memory device write speed vs. raw storage reliability trade-off at the physical layer and runtime data access workload dynamics at the system level. Leveraging runtime data access workload variation, we can opportunistically slow down NAND flash memory write speed and hence improve NAND flash memory raw storage reliability. This naturally enables an opportunistic use of weaker error correction schemes that can directly reduce SSD read access latency. We develop a disk-level scheduling scheme to effectively smooth the write workload in order to maximize the occurrence of runtime opportunistic NAND flash memory write slowdown. Using 2 bits/cell NAND flash memory with BCH-based error correction correction as a test vehicle, we carry out extensive simulations over various workloads and demonstrate that this developed cross-layer co-design solution can reduce the average SSD read latency by up to 59.4% without sacrificing the write throughput performance.

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Section: Introductionmentioning

confidence: 99%

Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes

Xie

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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“…Because the level-to-level V TH margin is narrower in the MLC than the single-level cell (SLC), small threshold voltage variation can induce a read error. [16][17][18][19][20][21] In this paper, we investigate the threshold voltage disturbance caused by the programmed adjacent cell in virtual source/drain NAND flash memory devices. By the device simulator, we simulate the VSD NAND flash memory device and observe the threshold voltage disturbance.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory

Kim¹,

Kwon²,

Ji³

et al. 2011

Jpn. J. Appl. Phys.

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In this paper, we investigate the threshold voltage disturbance caused by programmed adjacent cells in virtual source/drain (VSD) NAND flash memory device. The fringing field induced by charge in an adjacent memory node inhibits the inversion of virtual source/drain region. So, it increases the threshold voltage of the read cell. This is a drawback for the multi-level cell (MLC) operation. The device simulation and measurement data of fabricated devices show that the disturbance increases as the cell gate length and VSD length decreases. It can be minimized by the electric field concentration induced by the arch shape structure.

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Scaling in floating-gate non-volatile memory technologies and its implication on reliability

Tao

2009

2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

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Three bits per cell floating gate NAND flash memory technology for 30nm and beyond

Cited by 8 publications

References 4 publications

Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes

Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes

Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory

Scaling in floating-gate non-volatile memory technologies and its implication on reliability

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