Three-dimensional CMOS IC's Fabricated by using beam recrystallization

Kawamura, S; Sasaki, N.; Iwai, Tsuruji; Nakano, M.; Takagi, Mikio

doi:10.1109/edl.1983.25766

Cited by 64 publications

(7 citation statements)

References 7 publications

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“…In references [14] and [15], it had been mentioned that the driving force is related to the changes in enthalpy of formations (ΔH). Although ΔH is usually considered to be weakly dependent on pressure, it may have a significant effect on the IMC driving force.…”

Section: Mpamentioning

confidence: 99%

Effect of bonding pressure on the bond strengths of low temperature Ag-In bonds

Made

Gan

Lee

et al. 2008

2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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Bonding of multiple indium-silver intermediate layers facilitates precise control of the formed alloy composition and the joint thickness. The bonding temperature and post-bonding remelting temperature can thus be easily designed by controlling the multilayer materials and structure thicknesses. However, joining different materials involves the formation of intermetallics, which is known to be brittle. In this paper, In-Ag intermetallic phase formation under different applied pressure is studied.

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Section: Mpamentioning

confidence: 99%

Effect of bonding pressure on the bond strengths of low temperature Ag-In bonds

Made

Gan

Lee

et al. 2008

2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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“…MOS transistors fabricated on polysilicon exhibit very low surface mobility values (of the order of 10 cm 2 /(V.s) ), and also have high threshold voltages (several volts) due to the high density of surface states (several 10 12 cm -2 ) present at the grain boundaries. To enhance the performance of such transistors, an intense laser or electron beam is used to induce re-crystallization of the polysilicon film [6,[11][12][13][14][15][16], to reduce or even eliminate most of the grain boundaries. This technique however may not be very practical for 3-D devices because of the high temperature involved during melting of the polysilicon and also due to difficulty in controlling the grain size variations [17].…”

Section: Laser Crystallizationmentioning

confidence: 99%

3-D ICs: Motivation, performance analysis, technology and applications

Saraswat

2010

2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

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Interconnect delays, bandwidth and power consumption are increasingly dominating IC performance due to increases in chip size and reduction in the minimum feature size, in spite of new materials like Cu with low-k dielectric. Thereby severely limiting chip performance unless a paradigm shift from present interconnect architecture is introduced. One such promising technique is three-dimensional (3-D) ICs with multiple active Si layers and vertical interconnects. This paper presents a comprehensive review of 3-D ICs with multiple semiconductor layers. It is shown that significant improvement in performance and reduction in wire-limited chip area can be achieved with 3-D ICs if some long horizontal interconnects can be replaced by short vertical inter-layer interconnects. We also address the thermal concerns due to increased power density for 3-D circuits. Finally, an overview of some of the processing techniques which can be used to fabricate these circuits, is reviewed.

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“…With the initial attempts starting in 1980s, a number of techniques have been developed. Examples of early techniques include the use of polysilicon [4], recrystallization [5], [6], and microbumps [7], [8]. Each of these has its own advantages and disadvantages.…”

Section: Introductionmentioning

confidence: 99%

Low-Temperature Polymer-Based Three-Dimensional Silicon Integration

Kim

Xue

Tiwari

2007

IEEE Electron Device Lett.

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We describe a low-temperature polymer-based 3-D integration technique for wafer-scale transplantation of micrometer thick circuit and device layers onto another host wafer. The maximum temperature of this approach is 340 • C. It incorporates a low-k semiconductor compatible dielectric bonding media, employs tools that are readily available within a fabrication environment, and is very simple to implement. Another unique characteristic of the approach is the simultaneous separation of the transplanting layer from the donor assembly with the bonding to the host assembly. Alignment registration of several micrometers between device layers is demonstrated. Electrical results of 3-D inverter circuit along with demonstration of four-device-layer 3-D integrated stack are presented. Index Terms-Silicon-on-insulator (SOI), system-on-chip integration, 3-D IC, 3-D integration.

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Three-dimensional CMOS IC's Fabricated by using beam recrystallization

Cited by 64 publications

References 7 publications

Effect of bonding pressure on the bond strengths of low temperature Ag-In bonds

Effect of bonding pressure on the bond strengths of low temperature Ag-In bonds

3-D ICs: Motivation, performance analysis, technology and applications

Low-Temperature Polymer-Based Three-Dimensional Silicon Integration

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