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Laser‐recrystatiization is the best way to fabricate SOI for 3D IC's. Low source‐to‐drain leakage current as small as 3fA/μm is obtained for the SOI MOSFET's with the simple unseeded recrystallization containing grain boundaries. For the 3D CMOS static RAM's, packing density ratio to the conventional 2D CMOS static RAM's is given by 2n/3. and process steps ratio is given by n/3, where n is the device stacking number. The yield and cost OF 3D 1C's are analyzed. The cost of 3D IC's is less than that of 2D IC's at least by a factor of two for static CMOS RAM's, if the yield is determined by such random defects as accidental fine particles. The reason of this is that 3D 1C's do not require some process steps, which are necessary for 2D 1C's to differentiate between n‐ and p‐channel MOSFET's in a single device level.