Three dimensional simulation of short channel effects in junction less FinFETs

Abstract

In this article, n‐channel junction‐less transistors (JLTs) with gate lengths in the range of 20–250 nm, having crystalline‐silicon (c‐Si) and polycrystalline‐silicon (poly‐Si) channels are characterized for the short channel effects (SCEs). The shift of the threshold voltage with the gate length and the drain induced barrier lowering (DIBL) are determined by three dimensional numerical simulations using technology computer aided design (TCAD) software. Conductive channels are considered to be fin like structures surrounded by oxides and gate materials on three sides. The effect of important device parameters are considered. Degradation of SCEs with shortening of the gate length is predicted as expected from two dimensional simulations. In addition, simulations indicate improvements for lower doping. Thinner channels show better DIBL and threshold shift. The fin height dependence is more complicated where undesirable peak in DIBL is observed for mid‐range heights near 200 nm. DIBL sharply drops for lower fin heights but the threshold shift becomes worse. Overall a small gate device of 20 nm with short fins of similar size can be expected to give a threshold shift of less than 30 mV and DIBL about 70 mV/V and, the use of three dimensional dielectric pockets leads to near zero shift of the threshold voltage. The performance of the two material types are comparable.