Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs

Abstract

A novel method for realizing arrays of vertically stacked (e.g., ×3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The Gate-All-Around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high I on /I off ratio (~10 7 ), and low leakage current. Vertical stacking economizes on silicon estate and improves the onstate I DSAT at the same time. Both n-and p-FET devices are demonstrated.INTRODUCTION Driven by their unique properties, semiconductor nanowires (NW) are emerging to be a major research focus in nanotechnology area. Nanowire-based MOSFETs are projected as the candidates for end-of-the-roadmap devices for CMOS technology because they provide excellent electrostatic gate control of the channel. Various methods of achieving pseudo-1D semiconductor nanowires [1-6] such as vapor-liquid-solid mechanism, MOCVD/CVD, MBE, etc. have been reported. These include the Au-nano cluster initiated nucleation for axially elongated Ge epitaxial core nanowires with i-Ge shell [7] and Si shell [8], as recently reported by Harvard University group. Typically, these CVD grown NWs are randomly spread over the substrate, and it needs complicated techniques to integrate them in a device architecture for achieving specific functionalities. Some of the techniques reported for this purpose are 'pick-and-place' with AFM tip [9], liquid suspension, electric-or magnetic-field schemes [6], or fluid flow [10] etc. Such processes lack control in precision, repeatability, and scalability. Further, these methods are far from being capable of building nanowire network in a 3D-stack configuration in an orderly manner. On the other hand, using CMOS technologies, multi-bridge Si channel devices have been fabricated with SiGe sacrificial layers [11][12][13].In this paper, we present, for the first time, a novel method to make SiGe nanowire arrays which are vertically stacked and laterally spread out. We demonstrate gate-all-around (GAA) MOSFETs with excellent device characteristics using these nanowire arrays as the channel. Array architecture results in the saving of the Si real estate while boosting performance. It is worthwhile to mention that these devices have excellent potential of integration with Nano-Electro-MechanicalSystems (NEMS) on the same chip. Fig. 1 shows the process flow for the fabrication of nanowire arrays. Epitaxial layer of Si and Ge were alternately deposited on an 8" SOI wafer using a cold wall UHVCVD reactor. Thicknesses of Si layers are 50nm while that of Ge layers are 60 nm each. Growth of Ge layer is a two-step epitaxy process wherein a thin SiGe buffer layer deposition always precedes the growth of 100% Ge layers. Fig. 2 shows SEM image of the multilayered stack. After multilayer deposition, fin structures were patterned using 248nm KrF lithography. Alternating-Phase-Shift mask was used to pattern ultra narrow (~60 nm) fins. The fins were etched using reactive-ion-etch...

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

“…The vertically stacked wires MOSFET architecture pushes further the scaling limits of the CMOS technology [1][2][3][4]. Now deemed as a possible extension to FinFET, it offers multiple benefits.…”

Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs

“…Moreover, to increase the drive current per unit area with the higher density for integration, vertical stacking of NWs enables the use more available silicon surface per device [2][3][4][5]. Recently, short-channel GAA-SNW FETs have been successfully fabricated with diameter of less than 10 nm using several top-down CMOS compatible processes; they successfully suppress the short-channel effects [6][7][8][9].…”

III-V gate-all-around nanowire MOSFET process technology: From 3D to 4D

“…Furthermore, although lateral (parallel to the wafer surface) integration of NWs has been demonstrated with high drive current per wire, the overall current drivability of the devices is still limited by the pitch of the NWs. To overcome the bottleneck of drive current, for the first time, a top-down process technology has been developed to fabricate vertically stacked (normal to the wafer surface) III-V NWFETs, similar to some explored Si NWFETs [2][3] . We call this new type of NW devices III-V 4D transistors to distinguish them from III-V 3D transistors [1] which has only one vertical layer and multiple lateral wires.…”