Threshold voltage modeling for a Gaussian-doped junctionless FinFET

Kaundal, Shalu; Rana, Ashwani K.

doi:10.1007/s10825-018-1285-7

Cited by 10 publications

(2 citation statements)

References 22 publications

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“…This design choice implies a more complex fabrication process with respect to the bulk structure [5]. The designer could follow different approaches in order to optimize junctionless FinFETs: work function engineering of the gate to reduce I o f f (by changing the gate work function from 4.5 eV to 5.4 eV, I o f f can be reduced by five order of magnitudes) [7]; spacer engineering to improve performance (e.g., dual-k spacers architecture can provide an improvement in I on by 72.5% and in DIBL by 37.8%) [9]; doping engineering by using a Gaussian doped channel, which can lead to an increase in I on by 21.1% [10,13], or a lightly doped channel, which allows for better gate control on the device [11]; gate oxide engineering to provide higher performance (in terms of I on /I o f f and DIBL) by the implementation of complex hetero gate oxide structures [8]. For example, the double hetero gate oxide (DHGO) presented in Figure 9 can obtain a higher I on /I o f f with respect to conventional and triple/quadruple hetero gate oxide (THGO/QHGO) structures.…”

Section: Finfetmentioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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Section: Finfetmentioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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“…Recently, the JLMOSFETs have received significant attention for their technological feasibility and theoretical modeling. In the last decades, several device architectures for JLMOSFETs were proposed, such as Thin Film JLMOSFET [5], [6], FinFET [7], [8], Tunnel FET [9], [10], gate-all-around (GAA) FET [11], [12], singlegate JLT (SG-JLT) [13], [14], double-gate JLMOSFETs (DG-JLMOSFETs) [15]- [18], etc. The DG-JLMOSFETs are becoming more promising due to their superior performances in high speed and low power applications [19].…”

Section: Introductionmentioning

confidence: 99%

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

Islam

Hasan²,

Islam

et al. 2021

IEEE Access

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In this paper, the performance of GaAs and GaSb based sub-10 nm double-gate junctionless metal-oxide-semiconductor field-effect transistors (DG-JLMOSFETs) have been studied for highperformance switching applications. The quantum transmitting boundary method (QTBM) has been considered for electron transport, and the band structures are accounted for sp3d5s * tight-binding modeling. The channel thickness, t ch is varied from 1.7 to 4.7 nm to evaluate the device figure of merits (FOMs). The thinner channel's device shows a lower OFF-state current, while the ticker channel device allows a higher ON-state current. The threshold voltage is approximately 0.4 V for GaAs DG-JLMOSFETs with t ch = 1.7 nm, whereas it reduces to ∼0.05 V for that of t ch = 4.7 nm. Similar characteristics have been shown in GaSb devices. Besides, a significant impact of t ch on the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) is found in GaSb DG-JLMOSFETs compared with those of GaAs devices. The devices show a higher leakage-power dissipation in both channel materials and low-intrinsic delay for thicker t ch due to a substantial amount of energy drop. The above results indicate that III-V-based DG-JLMOSFETs are very promising for next-generation high-performance switching technology.INDEX TERMS GaAs, GaSb, double gate, junctionless MOSFETs, nano-scaled device, short-channel effects (SCEs), high-performance switching.

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The improved RF/stability and linearity performance of the ultrathin-body Gaussian-doped junctionless FinFET

Manikandan

Balamurugan

2020

J Comput Electron

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Threshold voltage modeling for a Gaussian-doped junctionless FinFET

Cited by 10 publications

References 22 publications

Junctionless Transistors: State-of-the-Art

Junctionless Transistors: State-of-the-Art

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

The improved RF/stability and linearity performance of the ultrathin-body Gaussian-doped junctionless FinFET

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