Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer

Abstract

First part of this paper discusses decoupling method limitation within the Power Delivery Network of a classical circuit and challenges introduced by 3D integrated circuit in term of power management. Solutions are exposed, such as integration of decoupling capacitor on silicon interposer.Second part of the paper focuses on the Through Silicon Capacitor (or TSC) as an alternative decoupling solution cointegrated with Through Silicon Vias on silicon interposer. TSC realization is described and architectural benefits of adding a partial copper-filling prior to the Metal-InsulatorMetal stack deposition are discussed.A distributed analytical model is used to quantify partial filling resistance contribution, pointing out a 6 decade decrease in ESR value of the structure. TSC process and matrix design parameters impact on capacitance density are studied. Finally, electrical performances of TSC modules are evaluated showing a low intrinsic impedance behavior granted by TSC parallel structure.

Modeling and Frequency Performance Analysis of Through Silicon Capacitors in Silicon Interposers

“…Inspired from the through silicon vias (TSV), a very promising technology seems to be the "through silicon capacitors" (TSCs), i.e., vertical cylindrical capacitors embedded through the silicon interposer. They are investigated in [6] and present high capacitance density (up to 35 nF/mm 2 ). High capacitance values are given by the use of a large amount of TSCs connected in parallel as a matrix.…”

3D ICs: An opportunity for fully-integrated, dense and efficient power supplies

“…an on-board solution ( Fig. 1, left scheme) fails to meet the fast power demand of the different supply domains in the multi-core system mainly due to the trace impedance [9]. Moreover, the N off-chip converters around the N-core processor occupy a large area on the PCB and need numerous power pins.…”

“…This paper aims to compare the 2D and 3D approaches using one or multiple active and passive layers to improve the achievable efficiency of the integrated power supplies of a multi-core processor. The 65nm bulk (mature, high yield), 28nm FDSOI (dense integration, large DVFS capability [8]) process and a potential TSC technology in a passive layer (high capacitance density [9]) are studied in this paper. This comparison leads to the key question: how much area is needed to integrate power supplies from this combination of three technologies to reach targeted power efficiency?…”

Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposer

“…This final integration has the advantage of sharing common steps with the TSV realization: DRIE etching, passivation, copper and polymer filling, backside contact. This co-integration with TSVs leads to an overall cost reduction of the process [6].…”

“…Nevertheless, the equivalent series resistance can be high due to conductor materials low conductivity. Newly developed 3D decoupling capacitors, named Through Silicon Capacitors (TSCs), are investigated in [6]. Those TSCs present high capacitance density (up to 56 nF/mm²), associated to low parasitic resistance thanks to the technological breakthrough use of copper in the structure.…”