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First part of this paper discusses decoupling method limitation within the Power Delivery Network of a classical circuit and challenges introduced by 3D integrated circuit in term of power management. Solutions are exposed, such as integration of decoupling capacitor on silicon interposer.Second part of the paper focuses on the Through Silicon Capacitor (or TSC) as an alternative decoupling solution cointegrated with Through Silicon Vias on silicon interposer. TSC realization is described and architectural benefits of adding a partial copper-filling prior to the Metal-InsulatorMetal stack deposition are discussed.A distributed analytical model is used to quantify partial filling resistance contribution, pointing out a 6 decade decrease in ESR value of the structure. TSC process and matrix design parameters impact on capacitance density are studied. Finally, electrical performances of TSC modules are evaluated showing a low intrinsic impedance behavior granted by TSC parallel structure.

The feasibility of cointegration of new capacitors, named "through silicon capacitors" (TSCs) with "through silicon vias" in silicon interposers has recently been demonstrated. Two architectures of TSC are extensively investigated in this paper: "axial TSC" whose electrodes are connected on either sides of the silicon interposer and "radial TSC" with electrodes both connected to the metal layers of the back end of line. A general modeling method based on distributed cell segmentation is proposed for both architectures. Validation is performed by measurements from 1 kHz to 40 GHz (above the resonance frequency of the components). A comparative study between radial and axial architectures is performed, leading to the prediction of the performances of those new components. Finally, design rules are established for future integration for power delivery networks decoupling applications.

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Inspired from Through Silicon Vias (TSVs), Through Silicon Capacitors (TSCs) are newly developed capacitors integrated throughout the silicon interposer. This paper deals with a demonstrator which investigates the first process steps of TSCs. A predictive modeling method of the impedance of large matrices of such components is proposed. The modeling method makes use of 2D/3D parasitic extraction software for the modeling of each parts of the structure. The resulting lumped RLCG parameters are used to generate a global equivalent circuit composed of segments of coupled distributed cells. The modeling method is validated by experimental results on the whole frequency range of use (up to 10 GHz). Such components demonstrate simultaneously high capacitance density (up to 23 nF/mm²), low parasitic equivalent series resistance and inductance and high serial resonance frequency (in GHz range for a capacitance value of 10 nF).