Through-the-gate-implanted ultrathin gate oxide MOSFET's with corner parasitics-free shallow-trench-isolation

DRAM Cell with High Signal Charge and Small Storage Capacitance Using the Gain Concept

“…When processing the shallow trench isolation (STI) after poly deposition [6,7], the cell requires a minimum area of 8F². This equals the minimum cell size of conventional DRAM cells, but this gain memory cell has the advantage of a significantly reduced storage capacitor.…”

Gate dielectrics: process integration issues and electrical properties

“…The scaling of gate dielectric thickness is a major challenge for future ULSI CMOS technologies. Only by taking advantage of in-situ gate stack processing and advanced CMOS process architectures, excellent CMOS device characteristics could be achieved with ultra-thin (1.6 nm) SiO 2 gate dielectric [1]. However, the gate oxide thickness has to be scaled down aggressively much further into the sub-1 nm regime within the next decade, according to the ITRS roadmap [2].…”

Process Integration of Crystalline Pr2O3 High-k Gate Dielectrics

“…Only by taking advantage of in-situ gate stack processing and advanced CMOS process architectures, excellent CMOS device characteristics could be achieved with ultra-thin (1.6nm) SiO 2 gate dielectric [1]. However, the gate oxide thickness has to be scaled down aggressively much further into the sub-1 nm regime within the next decade, according to the ITRS roadmap [2].…”