The influence of Vapor Phase Precleans leads to a different controllable fluorine content within the subsequently grown dielectric. The influence of the clean is discussed for non-volatile memory devices, advanced MOS transistors and ultra thin gate dielectrics. On the one hand, the Qw values for in situ cleaned samples are lower than for wet cleaned samples. Performing cycle stress on the EEPROM devices, the tunnel oxide (7.5nm) degrades the quicker with the increase in fluorine concentration within the oxide. On the other hand, MOS transistor characteristics show a significant improvement on the negative bias temperature instability (NBTI) in the PMOS threshold voltage. MOS transistors with ultra thin gate dielectrics (1.5nm) show the expected significant increase of the saturation current compared with 0.35gm technology (to 0 -=7.5nm). Excellent times until soft breakdown for ultra thin dielectrics are found when the in situ cleaning is used.

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