Throughput modeling to evaluate process merging transformations in polyhedral process networks

Meijer, Onno C.; Nikolov,; Stefanov, Todor

doi:10.1109/date.2010.5456953

Cited by 23 publications

(20 citation statements)

References 12 publications

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“…Consequently, if two processes are mapped onto the same architectural component, they are merged into a single process in the KPN, as is illustrated in Figure 2. higher) than the performance of a mapping in which each task is mapped onto a different processor [13]. Subsequently, to assess the performance of a mapping decision, we perform throughput analysis on the transformed KPN.…”

Section: Modeling Application Mappings As Merged Kahn Process Nementioning

confidence: 99%

“…Our throughput analysis is based on and extends the work presented in [13], in which the solution approach for the overall KPN throughput modeling relies on calculating the throughput τ Pi of a process (i.e., node) P i for all KPN processes and propagation of the lowest process throughput to the sink process. Here, we use a depth first search to determine the order of the processes for propagating throughputs.…”

Section: A Process Throughput and Throughput Propagationmentioning

confidence: 99%

“…To the best of our knowledge, current research on throughput analysis of KPNs has not addressed the handling of cycles. In [13], the authors only consider acyclic KPN graphs. A preliminary process throughput analysis in case of dataflow loops is suggested in [15] in terms of mapping rules, but the proposed rules have never been elaborated nor verified.…”

Section: B Handling Cyclesmentioning

confidence: 99%

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Design space pruning through hybrid analysis in system-level design space exploration

Piscitelli

Pimentel

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-System-level design space exploration (DSE), which is performed early in the design process, is of eminent importance to the design of complex multi-processor embedded system architectures. During system-level DSE, system parameters like, e.g., the number and type of processors, the type and size of memories, or the mapping of application tasks to architectural resources, are considered. Simulation-based DSE, in which different design instances are evaluated using system-level simulations, typically are computationally costly. Even using high-level simulations and efficient exploration algorithms, the simulation time to evaluate design points forms a real bottleneck in such DSE. Therefore, the vast design space that needs to be searched requires effective design space pruning techniques. This paper presents a technique to reduce the number of simulations needed during system-level DSE. More specifically, we propose an iterative design space pruning methodology based on static throughput analysis of different application mappings. By interleaving these analytical throughput estimations with simulations, our hybrid approach can significantly reduce the number of simulations that are needed during the process of DSE.

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Section: Modeling Application Mappings As Merged Kahn Process Nementioning

confidence: 99%

Section: A Process Throughput and Throughput Propagationmentioning

confidence: 99%

Section: B Handling Cyclesmentioning

confidence: 99%

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Design space pruning through hybrid analysis in system-level design space exploration

Piscitelli

Pimentel

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…The execution table update is done periodically, for example at the end of each iteration of the inner loop. To select, at runtime, which process needs to be helped, the helper scans the execution table and then chooses the highest execution time, since splitting is more beneficial when applied to the most computationally intensive process [14]. Once the helped is selected, the helper signals it setting a related flag in the corresponding entry of the execution table.…”

Section: Solutionmentioning

confidence: 99%

Online process transformation for polyhedral process networks in shared-memory MPSoCs

Meloni

Tuveri

Raffo

et al. 2014

2014 3rd Mediterranean Conference on Embedded Computing (MECO)

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In modern MPSoC architectures, programming to effectively exploit all the available resources becomes very challenging. Polyhedral Process Networks (PPN) are a known model of computation that represents a suitable solution for systematic mapping of parallel applications onto multiprocessor architectures. In previous works it has been shown that a given PPN program specification can be further analyzed and optimized, in order to meet the desired performance requirements. In this paper we present an online process splitting transformation that does not need a re-design of the communication patterns in network structure of the application. The novelty of our approach is that, differently from other compile-time approaches, the proposed transformation technique can be applied at run-time and followed, if needed, by the backward transformation. Using a FPGA-based MPSoC shared memory platform, we present an evaluation of the achievable performance improvements. We also discuss the overhead caused by the introduction of the run-time transformation support

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“…However, in contrast to most work dealing with synchronous dataflow graphs we do not consider only complete iterations [15,16], but allow partial repetition vectors. A special case of grouping firings results from clustering of SDF actors [3,12,23]. The result can be a quasi-statically scheduled system, in which the clustered actors can be modelled as scenarios of a weaklyconsistent SADF.…”

Section: Related Workmentioning

confidence: 99%

Performance analysis of weakly-consistent scenario-aware dataflow graphs

Geilen

Falk

Haubelt

et al. 2014

2014 48th Asilomar Conference on Signals, Systems and Computers

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The timed dataflow model of computation is a useful performance analysis tool for Electronic System Level Design automation and embedded software synthesis. It is used to model systems, including platform mapping and resource scheduling, of components communicating and synchronizing in regular patterns. Its determinism gives it strong analysability properties and makes it less subject to state-space explosion problems. Because of its monotonic temporal behaviour it can provide hard real-time guarantees on throughput and latency. It is expressive enough to cover a fairly large class of applications and platforms. The trend however, in both embedded applications and their platforms is to become more dynamic, reaching the limits of what the model can express and analyse with tight performance guarantees. Scenario-aware dataflow (SADF) is an extension that allows more dynamism to be expressed, introducing a controlled amount of non-determinism into the model to represent different scenarios of behaviour. The combination of a relatively infrequent switching between scenarios and still deterministic dataflow behaviour within scenarios stretches the expressiveness of the model while keeping sufficient analysability. In this report we investigate so-called weakly consistent graphs in which the scenario changes are not tightly coupled with periods of repetitive behaviour of the static dataflow behaviour in scenarios as in previous methods. We define their semantics in terms of (max, +) algebra and we introduce a method to analyse throughput using a generalisation of (max, +)-automata.

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Throughput modeling to evaluate process merging transformations in polyhedral process networks

Cited by 23 publications

References 12 publications

Design space pruning through hybrid analysis in system-level design space exploration

Design space pruning through hybrid analysis in system-level design space exploration

Online process transformation for polyhedral process networks in shared-memory MPSoCs

Performance analysis of weakly-consistent scenario-aware dataflow graphs

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