TID Response and Radiation-Enhanced Hot-Carrier Degradation in 65-nm nMOSFETs: Concerns on the Layout-Dependent Effects

Ren, Zhexuan; An, Xia; Li, Gensong; Liu, Jingyi; Xun, Mingzhu; Guo, Qi; Zhang, Xing; Huang, Ru

doi:10.1109/tns.2021.3063137

Cited by 5 publications

(1 citation statement)

References 22 publications

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“…Fig. 7 is drawn from Ren et al and depicts HCI degradation in irradiated and unirradiated devices in response to the bias condition described on the figure [18]. The test devices had a W/L = 0.2 µm/0.06 µm and were fabricated in an unspecified 65 nm technology.…”

Section: B Hot Carrier Degradation Comparison Between Stripe and Annu...mentioning

confidence: 99%

Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology

2023

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The design of countermeasures against integrated circuit counterfeit recycling requires the ability to simulate aging in CMOS devices. Electronic design automation tools commonly provide this ability; however, their models must be tuned for use with a specific target technology. This requires data which is ideally provided by a fab. It may also be collected from a set of purpose-built test devices, a costly and time-consuming process. Here we describe a novel, low-cost, and rapid approach to tuning such models. Our iterative method leverages public domain data sourced from published studies to fit an aging model. Results are statistically validated against the target technology's specification. We demonstrate our approach by fitting a compact hot carrier injection degradation model for use with both core and I/O nMOSFETs from a specific 65 nm technology. Our resulting model parameter values are validated with a maximum error of 0.5 % with a 99 % confidence bound.

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Section: B Hot Carrier Degradation Comparison Between Stripe and Annu...mentioning

confidence: 99%

Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology

2023

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Comparison of Total Ionizing Dose Effect on Tolerance of SCL 180 nm Bulk and SOI CMOS Using TCAD Simulation

Anjankar¹,

Dhavse

2022

Lecture Notes in Electrical Engineering

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Novel layout technique for single-event transient mitigation by the groove structure

Hao,

Chen,

Wang

et al. 2024

Radiation Effects and Defects in Solids

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TID Response and Radiation-Enhanced Hot-Carrier Degradation in 65-nm nMOSFETs: Concerns on the Layout-Dependent Effects

Cited by 5 publications

References 22 publications

Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology

Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology

Comparison of Total Ionizing Dose Effect on Tolerance of SCL 180 nm Bulk and SOI CMOS Using TCAD Simulation

Novel layout technique for single-event transient mitigation by the groove structure

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