TILE64 - Processor: A 64-Core SoC with Mesh Interconnect

Bell, Shane; Edwards, B.; Amann, John; Conlin, Rich; Joyce, K.; Leung, Vince; Mackay, J.; Reif, Mike; Bao, Liewei; Brown, Jeffery A.; Mattina, Matthew; Miao, Chyi-Chang; Ramey, Carl; Wentzlaff, David; Anderson, Walker; Berger, Ethan; Fairbanks, N.; Khan, Durlov; Montenegro, F.; Stickney, Jay; Zook, John

doi:10.1109/isscc.2008.4523070

Cited by 449 publications

(275 citation statements)

References 5 publications

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“…This introduces a serialization latency since the full context needs to be loaded (unloaded) into (from) the network: with 128-bit flit network and 3.1Kbits context size, the thread context consists of pkt size flit size = 26 flits, incurring the serialization overhead of 26 cycles. The context size will vary depending on the architecture; in the TILEPro64 [14], for example, it amounts to about 2.2Kbits (64 32-bit registers and a few special registers). Another overhead is the pipeline insertion latency.…”

Section: Performance Overhead Of Thread Migrationmentioning

confidence: 99%

The Execution Migration Machine: Directoryless Shared-Memory Architecture

et al. 2015

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Distributed directory cache coherence protocols for current many-core CMPs are not only difficult and error-prone to implement and verify, but also provide suboptimal performance when a thread requires access to large amounts of data distributed across the chip: the data must be brought to the core where the thread is running, incurring delays and energy costs. In this paper, we propose an approach based on the combination of partial-context thread migration and a directory-free remote access protocol: for these kinds of applications, our architecture can outperform directory-based cache coherence. In addition, unlike with distributed cache coherence protocols, the verification complexity of our architecture does not grow with the number of cores.

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Section: Performance Overhead Of Thread Migrationmentioning

confidence: 99%

The Execution Migration Machine: Directoryless Shared-Memory Architecture

et al. 2015

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“…A scalable directory-based cache coherence protocol called ACKwise using the above-mentioned optical network is implemented for ATAC processor. In addition, the TILE64 of Tilera Inc. [21] has been also provided as a commercial many-core processor. TILE64 combines 8 × 8 homogeneous cores using a mesh on-chip network.…”

Section: Related Workmentioning

confidence: 99%

A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards

Nguyen

Kondo

Hirao

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYNowadays, the trend of developing micro-processor with hundreds of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. Generally, three major issues required to be resolved includes: 1) realizing efficient massively parallel processing, 2) reducing dynamic power consumption, and 3) improving software productivity. To deal with these issues, we propose a solution to use many lowperformance but small and very low-power cores to obtain very high performance, and develop a referential many-core architecture and a program development environment. This paper introduces a many-core architecture named SMYLEref and its prototype system with off-the-shelf FPGA evaluation boards. The initial evaluation results of several SPLASH2 benchmark programs conducted on our developed 128-core platform are also presented and discussed in this paper.

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“…The low complexity 2D mesh has been used by most fabricated many-core systems including RAW [5], AsAP [6], TILE64 [7], AsAP2 [8] and Intel 48-core Single-Chip Cloud Computer (SCC) [9].…”

Section: Related Workmentioning

confidence: 99%

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Xiao

Baas

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its simplicity and the fact that processor tiles are traditionally square or rectangular, 2D mesh is mostly used for existing on-chip networks. However, efficiently mapping applications can be a challenge for cases that require communication between processors that are not adjacent on the 2D mesh. Motivated by the fact that applications often have largely localized communication patterns, we have proposed an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles, both of which increase local connectivity while keep much of the simplicity of a mesh-based topology. We have physically designed a 16-bit DSP processor and the corresponding processor arrays which utilize all three topologies. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application interprocessor communication distance reduction of 19%.

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TILE64 - Processor: A 64-Core SoC with Mesh Interconnect

Cited by 449 publications

References 5 publications

The Execution Migration Machine: Directoryless Shared-Memory Architecture

The Execution Migration Machine: Directoryless Shared-Memory Architecture

A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

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