Time-to-digital-converter based on multiple-tapped-delay-line

Chaberski, Dariusz

doi:10.1016/j.measurement.2016.03.065

Cited by 25 publications

(9 citation statements)

References 25 publications

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“…Therefore, the authors proposed a dual-sampling TDL architecture and a bin decimation method for Xilinx UltraScale FPGAs that could make the delay elements as small and uniform as possible, so that the implemented TDCs can achieve high time resolutions beyond the intrinsic cell delay [23,24]. Recently, selected, divided, or interpolated versions of the delay bin have become more popular to manage the nonuniform delay cells in FPGA-based TDCs, and thus to improve the time resolution and time linearity [22][23][24][25][26][27][28][29][30][31].…”

Section: Introductionmentioning

confidence: 99%

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Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

Chen

2018

Applied Sciences

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This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures.

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Section: Introductionmentioning

confidence: 99%

“…Two-stage inner interpolation methods that employ an eight-phase clock and an equivalent time coding delay line within a 28-nm FPGA chip were reported [25]. Although such methods enable high time resolution, the designs are highly complex.…”

Section: Introductionmentioning

confidence: 99%

Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

Chen

2018

Applied Sciences

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“…Cal_Run: After the Init state, the FSM runs the calibration in the Cal_Run state. In this state, 2 17 runs are executed to obtain the distribution of hits on the basis of the code density test. The hit counts are stored in the calibration memory Cal_Mem.…”

Section: Figurementioning

confidence: 99%

“…7 TDCs have been implemented in the analog domain by using application-specific integrated circuits (ASICs) capable of providing high time resolution. [17][18][19][20] However, a lack of uniformity in the delay cell of FPGA-based TDC implementations lowers the time resolution. Thus, numerous FPGA-based TDCs have been proposed recently.…”

Section: Introductionmentioning

confidence: 99%

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Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

Chen

2018

Circuit Theory & Apps

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In this study, we propose a robust field-programmable gate array (FPGA)-based time-to-digital converter (TDC) with run-time calibration. A code density test was used for differential nonlinearity (DNL) calibration to deal with nonuniformity in delay cells. The proposed calibration scheme is implemented as a four-step finite state machine (FSM) for run-time calibration. We implemented the TDC with the proposed run-time calibration circuit on the Xilinx 65-nm FPGA platform. This improved the DNL and integral nonlinearity (INL) values over those obtained using a TDC without run-time calibration circuit. The DNL and INL values at a time resolution of 46.875 picoseconds were [−0.68, 1.04] and [−4.27, 2.27] least significant bits, respectively. More than 30% DNL and INL improvements are achieved for the TDC with calibration circuit. The results obtained at temperatures of 27 • C to approximately 70 • C indicated that the proposed run-time calibration circuit enhanced the capability of the FPGA-based TDC against temperature effects. The FPGA-based TDC with the proposed run-time calibration FSM provides robust high-resolution performance suited for a range of scientific applications. KEYWORDS differential nonlinearity (DNL), field-programmable gate array (FPGA), run-time calibration, time-to-digital converter (TDC) Int J Circ Theor Appl. 2019;47:19-31.wileyonlinelibrary.com/journal/cta

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A new approach for pipeline time to digital converters based on analog interpolation and voltage amplification

Rezvanyvardom

Mirzaei

2019

Analog Integr Circ Sig Process

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Time-to-digital-converter based on multiple-tapped-delay-line

Cited by 25 publications

References 25 publications

Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

A new approach for pipeline time to digital converters based on analog interpolation and voltage amplification

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