2009 Asia and South Pacific Design Automation Conference 2009
DOI: 10.1109/aspdac.2009.4796456
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Time-to-Digital-Converter with small circuitry

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“…There are many TDC architectures [10][11][12], with various specifically targeting FPGA [8,9]. The simplest and commonly used approach is to use a counter registering the number of clock cycles since the beginning of the measurement.…”
Section: Time To Digital Convertermentioning
confidence: 99%
“…There are many TDC architectures [10][11][12], with various specifically targeting FPGA [8,9]. The simplest and commonly used approach is to use a counter registering the number of clock cycles since the beginning of the measurement.…”
Section: Time To Digital Convertermentioning
confidence: 99%