Timed Extensions for SDL

Bozga, Marius; Graf, Susanne; Mounier, Laurent; Ober, Iulian; Roux, Jean-Luc; Vincent, D

doi:10.1007/3-540-48213-x_14

Cited by 21 publications

(16 citation statements)

References 11 publications

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“…Specification and Description Language time management has been studied by several groups [28,29]. Specifically, [29] presented an extension that defines three kinds of transitions; (i) eager (consumed without delay), (ii) lazy (not urgent) and (iii) delayable (an enabling condition depending on time).…”

Section: Time and Priority Managementmentioning

confidence: 99%

Definition of Virtual Reality Simulation Models Using Specification and Description Language Diagrams

Casas

Pi²,

Garcia

et al. 2013

Lecture Notes in Computer Science

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Abstract.A full representation of a simulation model encompasses the behavior of the elements that define the model, the definition of the probability distributions that define the delays of the events that control the model, the experimental framework needed for execution, and the graphical representation of certain model elements. This paper aims to use specification and description language to achieve a full model representation by adding two extensions to the language, which allows for a complete and unambiguous definition of a discrete simulation model that is similar to a common discrete operations research simulation tool.

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Section: Time and Priority Managementmentioning

confidence: 99%

Definition of Virtual Reality Simulation Models Using Specification and Description Language Diagrams

Casas

Pi²,

Garcia

et al. 2013

Lecture Notes in Computer Science

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“…However, our design has a stricter timers semantics than that of SDL and is much more expressive than Erlang's (some nested timing patterns, which can be expressed in L, are not expressible in Erlang). There has also been some attempts at improving the timing abstractions in SDL for specification writers, such as the work in [15] on extending timers with annotations and supporting transitions with urgencies. Many other timed high-level languages exist [16,17,18].…”

Section: Related Workmentioning

confidence: 99%

Formal Specification and Analysis of Timing Properties in Software Systems

Alturki

Dhurjati²,

Yu³

et al. 2009

Lecture Notes in Computer Science

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Abstract. Specifying and analyzing timing properties is a critical but error-prone aspect of developing many modern software systems. In this paper, we propose a new specification language and analysis framework for expressing and analyzing timing behaviors of complex software systems. Our framework has the following significant benefits: a) it is expressive, b) it supports trace analysis and simulation of timing behaviors, c) allows for verification of properties of specification, and d) checks for common usage errors of timing constructs. The language constructs for timing were chosen to be very flexible, suitable for expressing different kinds of timing behaviors, and are inspired from timing constructs used in previous languages like SDL. We define the formal semantics of our language using a real-time rewrite theory. Since real-time rewrite theories are executable in Real-Time Maude, our framework supports trace analysis and simulation of timing behavior for specifications. Furthermore, the timed model checker for Real-Time Maude can be readily used for analyzing and verifying various real-time properties of the specifications. Finally, to prevent misuses of timing constructs that can be made possible due to their flexibility, we develop abstract interpretation based static analysis tools that check for common usage errors. We believe that our framework, with the above benefits, provides a significant step forward in facilitating the use of formal tools for specification and analysis of timing behaviors in software development.

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“…• Application to SDL: We illustrate how the above classes of timers can be defined and tested in SDL [4,22]. Once the FSM is extracted [3], the time extensions for SDL [12] have a natural representation in our model (Section 4).…”

Section: Ma Fecko Initiated the Timed Efsm Modelmentioning

confidence: 99%

“…[9,10]. The model uses exclusively the paradigm of EFSM, which makes it easily applicable to the languages such as SDL [4,22], VHDL [6], and Estelle [5], and thus enables testing timed systems with the numerous (E)FSM-based test generation methodologies [6,14,22].…”

Section: Timing Modelmentioning

confidence: 99%

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Towards Testing SDL Specifications: Models and Fault Coverage for Concurrent Timers

Fecko¹,

Duale²

2003

Formal Techniques for Networked and Distributed Systems - FORTE 2003

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Abstract.A recent model for testing systems with multiple timers is extended to compute proper input delays and timeout settings, and is applied to several types of timers required in a testing procedure. In the model, any transition in the specification can be made conditional on a set of running timers. Depending on the path taken to reach an edge, the values of the timer variables may render the traversal of the edge infeasible. The presented modeling technique, combined with the INconsistencies DEtection and ELimination (INDEEL) algorithms, allows the generation of feasible test sequences. The model also offers the flexibility to define timer lengths as variables, and have the INDEEL find the appropriate timer ranges. An approach to apply this new methodology to SDL timed extensions (guarding and delaying timers) is presented.

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Timed Extensions for SDL

Cited by 21 publications

References 11 publications

Definition of Virtual Reality Simulation Models Using Specification and Description Language Diagrams

Definition of Virtual Reality Simulation Models Using Specification and Description Language Diagrams

Formal Specification and Analysis of Timing Properties in Software Systems

Towards Testing SDL Specifications: Models and Fault Coverage for Concurrent Timers

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