Timing-driven row-based power gating

Abstract

In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In particular, we tackle here the two main issues involved in this methodology: (i) Clustering and (ii) the interfacing of power-gated and non power-gated regions within the same block. The clustering algorithm automatically selects an optimal subset of rows that can be power-gated with a tightly controlled delay overhead. We then address the issue of interfacing different gated regions and propose a novel technique to address this issue with minimal area and power penalty. Our approach is compatible with state-of-the art logic and physical synthesis flows and it does not significantly impact design closure. We achieve leakage power reductions as high as 89% for a set of standard benchmarks, with minimum timing and area overhead.

Power Gating to reduce Leakage Current in Low Power CMOS Circuits

“…To quantify the FoMs of power-gating, we adopted a flow based on the row-based methodology of [5]. The methodology realistically assumes that one or more rows are dedicated to the insertion of the sleep transistors and are appended at the end of the existing layout.…”

“…1.1 Clustering and Sizing: As discussed in [5], the clustering algorithm is based on using rows of the layout as atomic clustering objects. It takes two input parameters, namely, the performance (α) and the area (W sleep ) constraints.…”

Optimal MTCMOS reactivation under power supply noise and performance constraints

“…This prevents invalid output voltages during the idle state to be fed to the inputs of nonpower-gated cells, avoiding undesirable side-effects such as short-circuit currents and invalid latching. Alternatively, a pull-up pMOS can be inserted on the virtual ground [4], as shown in Figure 7. After the sleep transistor is turned-off, the pull-up rapidly charges the virtual ground rail to vdd, thus forcing a HIGH logic value to the output of all the connected cells.…”

“…Several embodiments of power-gating do exist. Main differentiation factors include: granularity at which the sleep devices are inserted; methods for sleep transistor sizing under timing/area constraints; physical device implementation (see, for instance, [1]- [4]). One important concern in practical power-gating is the control of the transient currents associated to the transition between the stand-by and the active state (i.e., reactivation or turn-on or wake-up).…”

Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting

“…In [1] authors propose to separate timing critical standard cells from the non-critical ones by placing them in different rows and by doing the power gating only for the non-critical standard cell rows. They have shown that a high leakage saving can be achieved while losing a small amount of performance.…”