Top-down pass-transistor logic design

Yano, Kazuo; Sasaki, Y.; Rikino, K.; Seki, Kazuhiko

doi:10.1109/4.509865

Cited by 207 publications

(89 citation statements)

References 19 publications

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“…Note that our approach is orthogonal to the approach of [22] in that, decomposed BDDs can be used to obtain a compact, BDD representation of the circuit. Each individual BDD can then be optimized by the techniques presented in this work and then mapped to a transistor-level circuit with appropriate buffering using [22].…”

Section: Ptl Network and Decomposed Bddsmentioning

confidence: 99%

“…Each individual BDD can then be optimized by the techniques presented in this work and then mapped to a transistor-level circuit with appropriate buffering using [22]. Similarly, optimization algorithms for area, delay and power presented here can be applied to BDDs generated using [17] as well.…”

Section: Ptl Network and Decomposed Bddsmentioning

confidence: 99%

“…For today's static CMOS it is known that transistor chains longer than 3-4 transistors in series can be unacceptably slow [12]. A monolithic BDD-based circuit would require buffer insertion as in [22] for all but the smallest circuits. In comparison, a decomposed BDD-based circuit where outputs of decomposition points are buffered allows us to exploit area gains (and the associated reduction in switching capacitance) while controlling the length of unbuffered chains.…”

Section: Performancementioning

confidence: 99%

“…A technique for generating PTL circuits in which buffers are inserted in the monolithic BDD to solve the speed problem is given in [22]. However, this approach still suffers from the BDD size problem.…”

Section: Ptl Network and Bddsmentioning

confidence: 99%

“…Clearly, the PTL design style can yield a circuit which can be much more compact than static CMOS. It was reported in [22] that the PTL yielded a 32% improvement in area, 29% improvement in delay and a 47% improvement in power over a static CMOS OR/NAND-based implementation of this function.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Logic synthesis for large pass transistor circuits

Buch

Narayan

Newton

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

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show abstract

Section: Ptl Network and Decomposed Bddsmentioning

confidence: 99%

Section: Ptl Network and Decomposed Bddsmentioning

confidence: 99%

Section: Performancementioning

confidence: 99%

Section: Ptl Network and Bddsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Logic synthesis for large pass transistor circuits

Buch

Narayan

Newton

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

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Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits

Shinogi¹,

Hayashi²,

Taki³

1999

Syst. Comp. Jpn.

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Pass‐transistor logic SPL has been introduced as a circuit structure to achieve lower power consumption of LSI, and its effectiveness has been confirmed. In the current study, the authors discuss a test generation method for using logic tests to detect stuck‐on faults of pass transistors in SPL. First, the authors discuss a technique for generating a logic discrepancy (D or ˜D) between a normal circuit and a faulty circuit in an SPL circuit, and a test generation procedure using this technique. Next, they discuss a technique to solve the problem of size explosion of a table, prepared in advance for this technique in order to obtain logic values in faulty circuits. Then, the authors propose DFT (design for testability) circuits featuring very low chip surface overhead and speed overhead, to improve the fault coverage. Finally, to demonstrate its effectiveness, the method was applied to benchmark circuits. © 1999 Scripta Technica, Syst Comp Jpn, 30(7): 55–68, 1999

show abstract

Test generation for stuck‐on faults in pass‐transistor logic SPL and implementation of DFT circuits

1999

View full text Add to dashboard Cite

Pass-transistor logic SPL has been introduced as a circuit structure to achieve lower power consumption of LSI, and its effectiveness has been confirmed. In the current study, the authors discuss a test generation method for using logic tests to detect stuck-on faults of pass transistors in SPL. First, the authors discuss a technique for generating a logic discrepancy (D or ~D ) between a normal circuit and a faulty circuit in an SPL circuit, and a test generation procedure using this technique. Next, they discuss a technique to solve the problem of size explosion of a table, prepared in advance for this technique in order to obtain logic values in faulty circuits. Then, the authors propose DFT (design for testability) circuits featuring very low chip surface overhead and speed overhead, to improve the fault coverage. Finally, to demonstrate its effectiveness, the method was applied to benchmark circuits. © 1999 Scripta Technica, Syst Comp Jpn, 30 (7): 5568, 1999

show abstract

Top-down pass-transistor logic design

Cited by 207 publications

References 19 publications

Logic synthesis for large pass transistor circuits

Logic synthesis for large pass transistor circuits

Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits

Test generation for stuck‐on faults in pass‐transistor logic SPL and implementation of DFT circuits

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