2017
DOI: 10.1109/tcad.2017.2650983
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ToPoliNano: A CAD Tool for Nano Magnetic Logic

Abstract: In the post-CMOS scenario, Field Coupled Nanotechnologies represent an innovative and interesting new direction for electronic nanocomputing. Among these technologies, NanoMagnet Logic (NML) makes it possible to finally embed logic and memory in the same device. To fully analyze the potential of NML circuits, design tools that mimic the CMOS design-flow should be used for circuit design.We present, in this manuscript, the latest and improved version of ToPoliNano, our design and simulation framework for Field … Show more

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Cited by 44 publications
(3 citation statements)
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“…Looking to propose more robust tools able to follow the top-bottom approach established by CMOS, [51] proposed the ToPoliNano, a tool that allows the description of NML circuits with high-level languages such as VHDL and Verilog HDL and, from that description, generates the circuit logicgate-based layout. This framework comprises two other tools: 1) MagCad and 2) ToPoliNano.…”
Section: A Field-coupled Nanocomputingmentioning
confidence: 99%
“…Looking to propose more robust tools able to follow the top-bottom approach established by CMOS, [51] proposed the ToPoliNano, a tool that allows the description of NML circuits with high-level languages such as VHDL and Verilog HDL and, from that description, generates the circuit logicgate-based layout. This framework comprises two other tools: 1) MagCad and 2) ToPoliNano.…”
Section: A Field-coupled Nanocomputingmentioning
confidence: 99%
“…Earlier clocking scheme models define partitions with sequential columns that repeat the clocking phase, ordering consistent signal propagation. Figure 8a depicts a 4-phase cutout and Figure 8b depicts a 3-phase cutout, both designed to work with combinational logic [37]. Figure 8b highlights the components of a basic cutout.…”
Section: Iic Clocking Schemesmentioning
confidence: 99%
“…The ToPoliNano tool designs iNML circuits and performs automatic layout generation and simulation. The circuits designed and validated by the tool in the literature are predominantly combinational circuits such as the half adder [9], full adder [10], multiplexer [11], demultiplexer [12], decoder [13], ripple carry adder [14], 32 bit Pentium-4 tree-Adder [15], ISCAS 85 benchmark [16], and systolic multiplier [17]. Sequential circuits have not been designed much in iNML.…”
Section: Introductionmentioning
confidence: 99%