Topology optimized mode conversion in a photonic crystal waveguide fabricated in silicon-on-insulator material

Abstract

We have designed and for the first time experimentally verified a topology optimized mode converter with a footprint of ~6.3 μm × ~3.6 μm which converts the fundamental even mode to the higher order odd mode of a dispersion engineered photonic crystal waveguide. 2D and 3D topology optimization is utilized and both schemes result in designs theoretically showing an extinction ratio larger than 21 dB. The 3D optimized design has an experimentally estimated insertion loss lower than ~2 dB in an ~43 nm bandwidth. The mode conversion is experimentally confirmed in this wavelength range by recording mode profiles using vertical grating couplers and an infrared camera. The experimentally determined extinction ratio is > 12 dB and is believed to be limited by the spatial resolution of our setup.

Binary particle swarm optimized 2 × 2 power splitters in a standard foundry silicon photonic platform

“…The high refractive index contrast in Si photonic platforms not only allows for compact device footprints but also makes possible device concepts that can take advantage of the strong optical confinement and scattering (e.g., grating couplers, micro-resonators, photonic crystals) [4][5][6]. The growing availability of foundry Si photonics, in combination with expanded computation capabilities for detailed electromagnetic simulations, open the opportunity to explore device designs that cannot be implemented in traditional, lower index contrast PIC platforms such as silica and compound semiconductors and are yet volume manufacturable.Device design performed by topology optimization without any a priori assumptions on the geometry has recently generated much interest [7][8][9][10]. As opposed to conventional design methodologies in which a few critical geometric parameters are tuned on a fixed geometry, topology optimization can find unexpected solutions with good performance within demanding constraints by exploring much larger parameter spaces.…”

“…An example is the polarization beam splitter of [9], which had a design footprint constraint of 2.4 μm × 2.4 μm. However, usual optimization approaches (e.g., in [8][9][10]) rely on highresolution rendering of intricate geometric features, such as through electron-beam lithography, which can result in designs that are incompatible with the design rules and minimum feature sizes in foundry processes, which use deep ultraviolet (DUV) photolithography.In this Letter, we investigate foundry fabrication of an optimization designed 2 × 2 3 dB power splitter. Power splitters are a common building block in PICs and, in Si photonic platforms, are typically implemented as multimode interference (MMI) couplers, directional couplers, and adiabatic couplers.…”

“…Device design performed by topology optimization without any a priori assumptions on the geometry has recently generated much interest [7][8][9][10]. As opposed to conventional design methodologies in which a few critical geometric parameters are tuned on a fixed geometry, topology optimization can find unexpected solutions with good performance within demanding constraints by exploring much larger parameter spaces.…”

Ultra-compact broadband higher order-mode pass filter fabricated in a silicon waveguide for multimode photonics

“…Being an integrated version of this technique, multimode photonics in silicon waveguides has attracted substantial attention [4][5][6][7] to exploit the already matured single-mode silicon photonic devices and silicon's complementary metal-oxidesemiconductor (CMOS) compatibility. For devices applied in the silicon multimode photonics, various functionalities have been achieved including (de)multiplexing [8][9][10][11], bending [12], converting [13], and resonating [14] multimode signals. Additionally, mode filtering is also foreseen as an essential functionality in silicon multimode photonics for mode-division multiplexing (MDM), resembling wavelength filtering for wavelength-division multiplexing (WDM).…”

“…Fully etched grating couplers [19] were used to couple light between the fibers and the silicon waveguides. Electron-beam lithography was utilized to pattern the chip and followed by an inductive plasma-etching process [13]. Finally, the whole chip was covered with a 1-μm SiO 2 layer.…”