Total-Dose Radiation and Annealing Studies: Implications for Hardness Assurance Testing

Winokur, P.S.; Sexton, F.W.; Schwank, J.R.; Fleetwood, D.M.; Dressendorfer, P. V.; Wrobel, T. F.; Turpin, D. C.

doi:10.1109/tns.1986.4334603

Cited by 94 publications

(11 citation statements)

References 12 publications

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“…1 we show ⌬N ot and ⌬N it for a p-MOS Oki transistor irradiated and annealed at V g ϭ6 V. During irradiation ͑time tϽ800 s͒, both ⌬N ot and ⌬N it increase significantly, as expected for these nonradiation-hardened devices. 20 Through subsequent 25°C annealing ͑800 sϽtϽ6 ϫ10 5 s͒, ⌬N ot decreases logarithmically with annealing time. 13,20 Values of ⌬N it first decrease slightly after irradiation, and then increase near the end of the 25°C anneal period.…”

Section: Correlation Between Latent Interface Trap Buildup and 1/f Nomentioning

confidence: 99%

“…20 Through subsequent 25°C annealing ͑800 sϽtϽ6 ϫ10 5 s͒, ⌬N ot decreases logarithmically with annealing time. 13,20 Values of ⌬N it first decrease slightly after irradiation, and then increase near the end of the 25°C anneal period. 9,10 When the annealing temperature is raised to 50°C ͑tϳ6ϫ10 5 s͒ and higher, the decrease in ⌬N ot accelerates with increasing anneal time and temperature.…”

Section: Correlation Between Latent Interface Trap Buildup and 1/f Nomentioning

confidence: 99%

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Correlation between latent interface trap buildup and 1/f noise in metal–oxide–semiconductor transistors

Johnson

Fleetwood

1997

Applied Physics Letters

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Articles you may be interested inSurface and core contribution to 1/f-noise in InAs nanowire metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 103, 033508 (2013); 10.1063/1.4813850Correlation between the 1 ∕ f noise parameters and the effective low-field mobility in Hf O 2 gate dielectric nchannel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 85, 1057 (2004); 10.1063/1.1779967 1/f noise in n-channel metal-oxide-semiconductor field-effect transistors under different hot-carrier stresses J. Appl. Phys. 86, 5203 (1999); 10.1063/1.371501 1/f noise measurements on indium antimonide metal-oxide-semiconductor field-effect transistors J. Appl. Phys. 85, 8485 (1999); 10.1063/1.370630 Near interface oxide trap capture kinetics in metal-oxide-semiconductor transistors: Modeling and measurements

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Section: Correlation Between Latent Interface Trap Buildup and 1/f Nomentioning

confidence: 99%

Section: Correlation Between Latent Interface Trap Buildup and 1/f Nomentioning

confidence: 99%

Correlation between latent interface trap buildup and 1/f noise in metal–oxide–semiconductor transistors

Johnson

Fleetwood

1997

Applied Physics Letters

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“…The initial design of the delay chain was Conservative to insure functionality. The lower dose rate allows the oxide trapped charge to anneal [17], which results in less change in the transistor characteristics. Variation in the read access time is reduced for the low dose rate case since the variation in the delay chain is reduced.…”

Section: Electrical Test Resultsmentioning

confidence: 99%

Design considerations for a radiation hardened nonvolatile memory

Murray¹

1993

IEEE Trans. Nucl. Sci.

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Sub-optimal design practices can d u c e the radiation hardness of a circuit even though it is f a b r i d in a radiation hardened process. This is especially true for a nonvolatile memory, as compared to a standafd digital circuit, where high voltages and unusual bias conditions m required. This paper will discuss the design techniques used in the development of a 64K EEPROM @ l e c W y Erasable Programmable Read Only Memory) to maximize radiation hardness. The circuit radiation test results will be reviewed in order to provide validation of the techniques

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“…However, it has been reported that annealing of the oxidetrapped charge component controls the threshold voltage shift, based on an analysis of transient annealing curves after large dose rate irradiation< 4 …”

Section: Ll Impulse Response Model For Threshold Voltage Shiftmentioning

confidence: 99%

Prediction Method for Total Dose Effects on Complementary Metal Oxide Semiconductor Integrated Circuits Using Impulse Response Model for Threshold Voltage Shift

Kamimura

Sakagami

1991

Journal of Nuclear Science and Technology

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A method is described to predict radiation hardness of general purpose CMOS logic lCs. The method uses an impulse response model for radiation-induced threshold voltage shift of an "elemental IC" selected from an IC family. The total dose degradation on !Cs can be predicted at any dose rate by simulations using the impulse response model of the threshold voltage shift and their circuit structure data. This method was applied to the prediction of radiation degradation of CMOS logic !Cs of HD74HC series, in which an inverter HD74HC04 was selected as the elemental IC. Four inverter samples were irradiated up to 100 Gy (Si) and then annealed to examine the impulse response of the threshold voltage shift of their n-and P-channel MOSFETs. Results predicted by this method represented the static characteristic degradation of the HD74HC04 irradiated up to a large total dose 1 kGy (Si) at two different dose rates 8 and 500 Gy (Si) /h.

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Total-Dose Radiation and Annealing Studies: Implications for Hardness Assurance Testing

Cited by 94 publications

References 12 publications

Correlation between latent interface trap buildup and 1/f noise in metal–oxide–semiconductor transistors

Correlation between latent interface trap buildup and 1/f noise in metal–oxide–semiconductor transistors

Design considerations for a radiation hardened nonvolatile memory

Prediction Method for Total Dose Effects on Complementary Metal Oxide Semiconductor Integrated Circuits Using Impulse Response Model for Threshold Voltage Shift

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