2010
DOI: 10.1109/ted.2010.2066568
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Total Performance of 32-nm-Node Ultralow-$k$/Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica $(k = \hbox{2.1})$

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Cited by 10 publications
(3 citation statements)
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“…The measured via resistance is effectively reduced by introducing each PET process. To analyze via-open failure, the voltage-contrast method 17) and TEM cross-sectional observation were carried out for the non-PET sample, and a failed via and a typical good via, shown in Figs. 13(a) and 13(b), respectively, are compared.…”
Section: Resultsmentioning
confidence: 99%
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“…The measured via resistance is effectively reduced by introducing each PET process. To analyze via-open failure, the voltage-contrast method 17) and TEM cross-sectional observation were carried out for the non-PET sample, and a failed via and a typical good via, shown in Figs. 13(a) and 13(b), respectively, are compared.…”
Section: Resultsmentioning
confidence: 99%
“…The issues of concern in dual-damascene integration of porous SiOCHs are: (1) the degradation of interconnect characteristics caused by dry etching, ashing, and wet cleaning, [16][17][18][19][20][21][22] (2) the degradation of trench shape by the barrier/seed sputtering process, i.e., resputtering, 23,24) (3) residues at the bottom of the via holes owing to the formation of large amounts of by-products during the dryetching process that are too hard to remove by wet cleaning, [16][17][18][19][20][21][22] and ( 4) film delamination due to the fragile, porous, low-k structure. 1,2) To solve these problems, postetching treatments using H 2 , N 2 , and CH 4 have been studied for the metal hard mask trench-first dual-damascene (D/D) process using porous SiCOH.…”
Section: Introductionmentioning
confidence: 99%
“…Many works have reported on low-k materials. [2][3][4][5][6][7] However, the fine patterning and metal filling processes are the most important technologies.…”
Section: Introductionmentioning
confidence: 99%