Toward automatic proof generation for information flow policies in third-party hardware IP

Bidmeshki, Mohammad-Mahdi; Makris, Yiorgos

doi:10.1109/hst.2015.7140256

Cited by 30 publications

(13 citation statements)

References 9 publications

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“…There exist several secure languages, enabling designers to model provably secure hardware. Caisson [31], Sapper [30], SecVerilog [7,40], and VeriCoq-IFT [5] are hardware security design languages that allow designers to label and track information low. Caisson [31] and Sapper [30] are both FSM-based languages that have been developed by combining domain-speciic abstractions common to hardware design and type-based techniques used in secure programming languages.…”

Section: Related Workmentioning

confidence: 99%

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Goli¹,

Drechsler

2024

ACM Trans. Embed. Comput. Syst.

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Virtual Prototypes (VPs) at the Electronic System Level (ESL) are being increasingly adopted by the semiconductor industry and play an important role in modernizing the System-on-Chips (SoCs) design flow to raise design productivity and reduce time-to-market constraints. Due to their early availability and significantly faster simulation speed in comparison to Register Transfer Level (RTL) designs, VPs are used as reference models for lower levels of abstraction. Leveraging VPs and extending their use-cases for early security validation are shown as a promising direction. As the cost of fixing any security flaws increases with the stage of development, VP-based security validation can significantly avoid costly iterations. In this paper, we present a novel VP-based dynamic information flow analysis approach at the ESL, consisting of three main phases which are run-time behavior extraction (in terms of transactions), transactions transformation, and security validation. The proposed approach empowers designers to validate the information flow policies of a given VP-based SoC against the most occurring security threat models which are information leakage (confidentiality) and unauthorized access to data in a memory (integrity). Experimental results including an extensive set of standard benchmarks and two real-world VP-based SoCs demonstrate the scalability and applicability of the proposed approach.

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Section: Related Workmentioning

confidence: 99%

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Goli¹,

Drechsler

2024

ACM Trans. Embed. Comput. Syst.

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“…The PCH-IP and VeriCoq projects provide several tools for verifying IP security and trust [245]- [247]. These tools define rules for converting RTL Verilog design to Coq 1 semantic circuit models.…”

Section: Hardware Security Tools a Security Verification Toolsmentioning

confidence: 99%

“…They use the Coq theorem prover to formally verify confidentiality properties on the Coq circuit models in order to detect malicious design modifications. VeriCoq [245] has recently been extended to the transistor level to verify the security of analog/mix-signal designs and detect analog HTs [281]. However, these projects tend to employ conservative rules to model information flow security behaviors, which can lead to false alarms in security verification.…”

Section: Hardware Security Tools a Security Verification Toolsmentioning

confidence: 99%

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Chang

Sengupta

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Hardware Trojans are small-scale circuits designed to perform a malicious operation not intended by the original system [ 18 ]. Attackers can insert them at multiple points in the supply chain, such as the foundry [ 19 ] or a third-party IP provider [ 20 ], as illustrated in Figure 3 . Various techniques have been developed to detect hardware Trojans during testing or at run-time in the field [ 21 ].…”

Section: Related Workmentioning

confidence: 99%

Malicious Activity Detection in Lightweight Wearable and IoT Devices Using Signal Stitching

Karabacak

Ogras

Ozev

2021

Sensors

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The integrated circuit (IC) manufacturing process involves many players, from chip/board design and fabrication to firmware design and installation. In today’s global supply chain, any of these steps are prone to interference from rogue players, creating a security risk. Therefore, manufactured devices need to be verified to perform only their intended operations since it is not economically feasible to control the supply chain and use only trusted facilities. This paper presents a detection technique for malicious activity that can stem from hardware or firmware Trojans. The proposed technique relies on (i) repetitious side-channel sample collection of the active device, (ii) time-domain stitching, and (iii) frequency domain analysis. Since finding a trusted sample is generally impractical, the proposed technique is based on self-referencing to remove the effects of environmental or device-to-device variation in the frequency domain. We first observe that the power spectrum of the Trojan activity is confined to a low-frequency band. Then, we exploit this fact to achieve self-referencing using signal detection theory. The proposed technique’s effectiveness is demonstrated through experiments on a wearable electronics prototype and system-on-chip (SoC) under a variety of practical scenarios. Experimental results show the proposed detection technique enables a high overall detection coverage for malicious activities of varying types with 0.8 s monitoring time overhead, which is negligible.

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Toward automatic proof generation for information flow policies in third-party hardware IP

Cited by 30 publications

References 9 publications

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Malicious Activity Detection in Lightweight Wearable and IoT Devices Using Signal Stitching

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