Toward Increasing FPGA Lifetime

Srinivasan, Suresh; Krishnan, R.; Mangalagiri, Prasanth; Xie, Yuan; Narayanan, Vijaykrishnan; Irwin, M.J.; Sarpatwari, K.

doi:10.1109/tdsc.2007.70235

Cited by 80 publications

(34 citation statements)

References 25 publications

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“…Many techniques have been explored to maximize lifetime in the presence of circuit aging with the aim of increasing period prior to initial failure [4], [6], [21]. For example in [6], different ASIC parameters such as supply voltage, operating clock frequency and cooling power are tuned using optimization algorithms to achieve power efficiency over lifetime as compared to traditional approach of incorporating worst case delays.…”

Section: Related Workmentioning

confidence: 99%

“…In other efforts for FPGAs, the in-field reconfigurability and uniformity of available resources is exploited. For example, [4] employs periodic replacement of same configuration and rerouting interconnects with high switching activities (based on design-time estimates) so as to age components of FPGA in a uniform manner. Similarly, wear-leveling strategies for FPGAs such as alternative placements to form multiple configurations at design-time are introduced in [21].…”

Section: Related Workmentioning

confidence: 99%

“…This process is analogous to traversing a tree structure starting from the leaf node, which is the PO in this case, until the root is encountered. For example, LUT D contributes to the generation of both POs out 1 and out 4 , whereas LUT K is only responsible for out 4 . To illustrate different scenarios in which the suspect resources are selected, two distinct failure cases are presented as shown in Figure 1.…”

Section: Fault Isolation Via Back Tracingmentioning

confidence: 99%

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Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

Ashraf

DeMara

2013

IEEE Trans. Comput.

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In this work, Field Programmable Gate Array (FPGA) reconfigurability is exploited to realize autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist Driven Evolutionary Refurbishment (NDER) technique utilizes design-time information from the circuit netlist to constrain the search space of the algorithm by up to 98.1% in terms of the chromosome length representing reconfigurable logic elements. This facilitates refurbishment of relatively large-sized FPGA circuits as compared to previous works. Hence, the scalability issue associated with Evolvable Hardware based refurbishment is addressed and improved. Experiments are conducted with multiple circuits from the MCNC benchmark suite to validate the approach and assess its benefits and limitations.Successful refurbishment of the apex4 circuit having a total of 1252 LUTs with 10% spares is achieved in as few as 633 generations on average when subjected to simulated randomly-injected single stuck-at faults. Moreover, the use of design-time information about the circuit undergoing refurbishment is validated as means to increase the tractability of dynamic evolvable hardware techniques.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Fault Isolation Via Back Tracingmentioning

confidence: 99%

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Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

Ashraf

DeMara

2013

IEEE Trans. Comput.

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“…Researchers have proposed various techniques to exploit such flexibility in FPGAs [1][2][3]. This paper focuses on aginginduced delay degradation in FPGA logic and routing resources and presents a physical planning and reconfiguration scheme to reduce aging-rate and delay degradation in FPGA resources.…”

Section: Introductionmentioning

confidence: 99%

Aging-aware high-level physical planning for reconfigurable systems

Ghaderi

Bozorgzadeh

2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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Due to advanced silicon technology, reconfigurable system-on-chip devices such as FPGAs are increasingly becoming sensitive to aging effects. This paper presents a high-level physical planning with reconfiguration strategy in order to mitigate the aging-induced delay degradation in FPGA resources. The proposed solution is an offline framework composed of an agingaware floorplanner coupled with a proactive aging-aware reconfiguration policy which generates checkpoints aperiodically for runtime reconfiguration. We consider BTI and HCI aging mechanisms and consider the BTI-based aging recovery during idle periods using aging history map. The experiments demonstrate that sequence of configurations generated by this scheme provides average aging-rate reduction on FPGA resources and application performance by 53.2% and 17.5%, respectively.

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“…Srinivasan [5] gives an impact analysis of two different types of hard errors on FPGAs and a study of the performance degradation of FPGAs over time caused by HCI and NBTI. An experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs has been presented in [6].…”

Section: Introductionmentioning

confidence: 99%