Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

Coudrain, P.; Colonna, Jean-Philippe; Aumont, C.; Garnier, G.; Chausse, P.; Segaud, R.; Vial, K.; Jouve, A.; Mourier, Therry; Magis, T.; Besson, P.; Gabette, Laurence; Brunet-Manquat, C.; Allouti, N.; Laviron, C.; Chéramy, S.; Saugier, E.; Pruvost, J.; Farcy, A.; Hotellier, N.

doi:10.1109/eptc.2012.6507102

Cited by 19 publications

(6 citation statements)

References 3 publications

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“…It is formed by the stacking of a 7.5 mm 2 chip (top die) on a 31 mm 2 chip (bottom die) using μ-bumps and TSV-middle in a face-to-back configuration, as commonly used for wide I/O products [9] (Figs. 1 and 2).…”

Section: Test Chipmentioning

confidence: 99%

Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

Souare

Fiori

Farcy

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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International audienceThis paper presents the impact of silicon thickness on the temperature and the thermal resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks to embedded in situ sensors and numerical design of experiments (DOEs). The primary objective is to provide the sensitivity of modeling factors by analyzing the variance on the basis of Sobol indices through DOE. The results show a strong influence of the silicon thickness and of the position of the hot spots with respect to the sensors on the maximum temperature and the thermal resistance of the total stack. The boundary conditions, in particular the heat-transfer coefficient of the bottom surface of the wafer, are also identified as significant factors. Therefore, simulation results and measurement approaches are compared. The measurements are carried out with embedded in situ sensors in the bottom die at wafer level. The results show a significant increase in temperature while decreasing the silicon thickness

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Section: Test Chipmentioning

confidence: 99%

Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

Souare

Fiori

Farcy

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…A copper pillar process flow, 20µm diameter, Cu/SnAg (µbumps) and Cu/Ni/Au (copper post) metallurgy, was chosen for topbottom die connection (figure 2) -A TSV-middle process, 10µm diameter and 80µm depth (Aspect ratio 8:1), and some copper pillar diameter 55µm, were chosen for die to package connection (figure 3). A face2Back flip chip assembly were needed, very similar to the one used for Wide I/O demonstrator [5]. One particularity of this stack is that both dies have strictly the same size.…”

Section: B Technology and Integrationmentioning

confidence: 99%

3D advanced integration technology for heterogeneous systems

Vivet

Bernard

Clermidy

et al. 2015

2015 International 3D Systems Integration Conference (3DIC)

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International audience3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description

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“…Fig. 2 brings additional circuit and technology information (further technology details can be found in [9]). Heaters and sensors placed at the center area (C1-C4) are indeed used to evaluate the impact of hotspots on the DRAM performance, while heaters placed at the bottom-left corner (BL1-BL4) are used to emulate a hotspot behavior produced by a quad-core processor.…”

Section: A Thermal Test Circuitsmentioning

confidence: 99%

“…There is, however, no thorough review of the thermal impact of the TSVbased 3D integration technology. This paper firstly evaluates the thermal impact of a WideIO compatible memory on a memory-on-logic 3D circuit, which is one of the drivers and most likely applications of the available 3D integration technology [9]. Silicon measurements validate thermal simulations and reveal the temperature profile of singledie and 3D versions of a thermal test circuit instrumented with integrated heaters and temperature sensors.…”

Section: Introductionmentioning

confidence: 99%

Thermal performance of 3D ICs: Analysis and alternatives

Santos

Vivet

Colonna

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphitebased heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45ºC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.I.

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Towards efficient and reliable 300mm 3D technology for wide I/O interconnects

Cited by 19 publications

References 3 publications

Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

3D advanced integration technology for heterogeneous systems

Thermal performance of 3D ICs: Analysis and alternatives

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