Towards the capability of providing power-area-delay trade-off at the register transfer level

Abstract

This paper presents a new register-transfer level (RTlevel) power estimation technique based on technology decomposition. Given the Boolean description of a circuit function, the power consumption of two typical circuit implementations, namely the minimum area implementation and the minimum delay implementation, are estimated, respectively. This provides a capability of obtaining a full power-delay-area trade-off curve at the RT level. Our method makes it possible to capture the structural and/or functional information of a circuit without going through actual gate-level implementation. Experimental results show that the accuracy is very reasonable. KeywordsRT-level, power estimation, entropy, technology decomposition INTRODUCTIONPower reduction has become one of the primary goals in the design of modern digital systems due to the increasing demand for low power circuits in portable applications. Increasing package and cooling cost is another driving factor. To achieve low power design, the designer has to explore the design space to make the appropriate powerarea-delay trade-off decision. Accurate power estimation at different abstraction levels is thus urgently needed to carry out the correct design space exploration.Recently several RT level power estimation methodologies were proposed based on entropy and information theoretic approaches [1,2]. However, these approaches are suffering from two main discrepancies. First, entropy of the function of the circuit is used to estimate the circuit switching activity as well as to model the area cost of a circuit [2][3][4]. Unfortunately, the accuracy of entropy-based power estimation is very limited since the capacitance model using entropy does not work well over a wide range of circuits. Secondly, these methods only give a single power estimate for a given functional description of the circuit. They use very little information about the function and complexity of the circuit at the behavioral level and also do not account for the effect of different potential circuit implementations for different requirements. In this paper, we are targeting to provide a capability to generate the power-area-delay tradeoff curve at the RT level. In particular, we propose a method to estimate the power consumption for the minimum area implementation (MAI) and the minimum delay implementation (MDI) given a functional description of a circuit. These are the two extreme points of the power-areadelay trade-off curve whose power estimation serves as a first step to generate the full trade-off curve.The remainder of the paper is organized as follows. In Section 3, we describe the power estimation technique for the MAI based on technology decomposition. We discuss the modeling of node distribution, capacitance distribution as well as entropy distribution for power estimation. Section 4 is devoted to the power estimation for the MDI, including the method of estimating the delay and the total capacitance for the MDI. Experimental results and discussions are provided in Section 5 and, ...

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