Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things

Kuo, F. S.; Ferreira, Sandro Binsfeld; Ron, Chen; Cho, Lan-Chou; Jou, Chewn-Pu; Chen, Mark; Babaie, Masoud; Staszewski, Robert Bogdan

doi:10.1109/mwsym.2018.8439369

Cited by 6 publications

(13 citation statements)

References 9 publications

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“…Compared with the DT-RX in [1], the power budget reduces nearly 50% due to the single-path architecture. Reference [20] operates at 0.275 V via an external voltage doubler and achieves 1-mW power consumption but with a 7-dB degradation of FoM compared with our work. Reference [7] has better selectivity due to an enhanced dynamic range of DPLL-based ADC by means of a feedback DAC.…”

Section: Resultsmentioning

confidence: 78%

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A Type-II Phase-Tracking Receiver

Chen

et al. 2021

IEEE J. Solid-State Circuits

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We present a new analog-to-digital converter (ADC)-based architecture of a phase-tracking receiver (PT-RX) optimized for ultra-low-power (ULP) and ultra-low-voltage (ULV) operations for the Internet of Things (IoT). The RX employs a type-II loop configuration that offers improved stability compared with the previous type-I PT-RX solutions. In addition, the type-II loop is also very tolerant of long run-lengths of consecutive "1" or "0" symbol sequences. Fabricated in 28-nm CMOS, the prototype PT-RX targets Bluetooth low energy (BLE) standard consuming only 1.5 mW at a supply of ≤0.7 V. It maintains an adjacent-channel rejection (ACR) of ≥−11/3.5/17/27 dB at 0/±1/±2/±3 MHz offset and can tolerate out-of-band (OOB) blockers of minimum −21 dBm across 1.0-3.5 GHz while also offering a best-in-class figure of merit (FoM) of 181 dB, with a 1-Mb/s BLE sensitivity of −93 dBm. Index Terms-Bluetooth low energy (BLE), digitally controlled oscillator (DCO)-based receivers (RXs), discrete-time (DT) filter, Internet-of-Things (IoT), phase-tracking RXs (PT-RXs), successive-approximation-register (SAR)-analog-to-digital converter (ADC), ultra-low power (ULP), ultra-low voltage (ULV). I. INTRODUCTION T HE massive deployment of Internet-of-Things (IoT) applications calls for ultra-low-power (ULP) and ultralow-voltage (ULV) design techniques for system-on-chip (SoC) devices realized in nanoscale CMOS [1]-[4]. The RF receiver (RX) is a key IoT subsystem that takes a significant portion of the IoT's total power budget. In the industry, commercial RXs using Cartesian [i.e., in-phase/quadrature (I/Q)] topology [5], [6] aimed at Bluetooth low energy (BLE), a dominant standard in IoT devices, consume 5-10 mW. A more recent industry work [1], a superheterodyne discrete-time (DT) Cartesian RX, achieves the lowest power of 2.75 mW with a sensitivity of −95 dBm. However, it becomes more and more challenging to further reduce the power allocation for the RX,

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Section: Resultsmentioning

confidence: 78%

“…An ADPLL in [19] runs its DCO at 0.23 V and a doubler at 0.35 V to power the voltage-sensitive TDC. Reference [20] demonstrates a DT-RX directly supplied at 0.275 V via an sw-cap-based voltage doubler. In this work, the RF front end is optimized at 0.3 V and a DCO at 0.25 V. A 0.7-V supply is applied to mixed-signal circuits.…”

Section: Circuit Implementationmentioning

confidence: 99%

A Type-II Phase-Tracking Receiver

Chen

et al. 2021

IEEE J. Solid-State Circuits

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“…Finally, in [10] a new class discrete receiver is realized. It is based in a discrete-time superheterodyne architecture and designed aiming a decrease in circuits' supply voltage proportional to technology node decrease.…”

Section: A Pgamentioning

confidence: 99%

Design of a Programmable Gain Amplifier (PGA) for Bluetooth Low Energy (BLE) in 0.13 um CMOS

Júnior¹,

Freire²,

Venuto³

2020

JICS

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Programmable Gain Amplifiers (PGA's) are circuits capable of conveniently changing their gain to address various levels of amplification. Knowing this, the topology proposed in this work takes a source degenerated first stage, a common-source with resistive load second stage, and a gm boosting circuit interface to realize a PGA that has low power consumption and low area. The design developed was able to achieve a maximum power dissipation of 103.1 uW, a minimum bandwidth of 5.59 MHz, a maximum noise of 32.01 nV/sqrt(Hz), and a gain range of 2.31 - 19.84 dB. Each differential output of the circuit is loaded with 700 fF, which is the estimated load for the hypothetical following block, the Analog-to-Digital Converter (ADC). Furthermore, the supply voltage of the circuit is 1 V and the design was undertaken on Global Foundrie's 130 nm technology. The phase margin of the core circuit is no greater than 100.3˚ and no less than 49˚ . The circuit which design is described in this work is intended to be within the receiver (RX) sub-domain of a Bluetooth Low-Energy (BLE) system, which finds applications on the IoT and healthcare industries, for instance.

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“…A smaller power dissipation, at the transmitter part, is obtained by using all-digital circuits (KUO et al, 2017;LIU et al, 2015) or operating at the ultra-low voltage range (ULV) (YIN et al, 2018). On the other hand, at the receiver (RX) part, the smaller power dissipation is obtained using modern Low-IF and Zero-IF architectures, operating with low voltage supply (ZHANG; MIYAHARA; OTIS, 2013; YI BRYANT;SJOLAND, 2014;SELVAKUMAR;LISCIDINI, 2015;DING et al, 2018;KUO et al, 2018), or by reducing the number of RF active blocks (MASUCH; DELGADO-RESTITUTO, 2013a; BRYANT; SJOLAND, 2014). The digital-intensive circuits transceivers should be implemented in advanced CMOS process (≤ 40 nm) in order to obtain faster switches and lower parasitic capacitances (KUO et al, 2018).…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, at the receiver (RX) part, the smaller power dissipation is obtained using modern Low-IF and Zero-IF architectures, operating with low voltage supply (ZHANG; MIYAHARA; OTIS, 2013; YI BRYANT;SJOLAND, 2014;SELVAKUMAR;LISCIDINI, 2015;DING et al, 2018;KUO et al, 2018), or by reducing the number of RF active blocks (MASUCH; DELGADO-RESTITUTO, 2013a; BRYANT; SJOLAND, 2014). The digital-intensive circuits transceivers should be implemented in advanced CMOS process (≤ 40 nm) in order to obtain faster switches and lower parasitic capacitances (KUO et al, 2018). Otherwise, the strategies based on cutting some active-RF hardware and reducing the operation voltage can also be implemented in low-cost sub-micron CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

Filtros RC-Ativo ULV e ULP combinando OTA de único estágio e transcondutância negativa de entrada para receptores RF de baixa energia.

Severo¹

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I would like to thanks to Professor Wilhelmus Adrianus Maria Van Noije for the opportunity in work as a Ph.D. candidate at the Polytechnic School of the University of São Paulo and by all the challenges imposed to me that have collaborated significantly in the improvements of my professional abilities. I would like to thanks to the Federal University of Pampa for the opportunity of being on leave from the university by 3.5 years that made possible working full time in the Ph.D. studies and to the CNPq research agency for support to this work. I would also like to thanks to professors João A. Martino e Paula G. Der Agopian for all the help in the CMOS transistor characterization, to the IMEC Free-mini@asic and to the MOSIS Educational programs for the free integrated circuit fabrications and to professors João N. Soares Júnior and Márcio C. Schneider for all the suggestions gave me at the qualification exam. I would like to thanks to all the members of the DMPSV department of the LSI at USP, especially to Silvana, for all the conversations at the coffee time and commemoration during my stay in São Paulo. Finally, I thanks to my wife Tanísia for all the help and understanding during this shortage of time phase of my life.

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Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things

Cited by 6 publications

References 9 publications

A Type-II Phase-Tracking Receiver

A Type-II Phase-Tracking Receiver

Design of a Programmable Gain Amplifier (PGA) for Bluetooth Low Energy (BLE) in 0.13 um CMOS

Filtros RC-Ativo ULV e ULP combinando OTA de único estágio e transcondutância negativa de entrada para receptores RF de baixa energia.

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