Transconductance/drain current based distortion analysis for analog CMOS integrated circuits

Abstract

This paper proposes a technique to analyze distortion in analog CMOS integrated circuits. The proposed technique captures a transistor's nonlinearity using a twodimensional Taylor series with coefficients that depend on the transconductance-to-current ratio (gm/ID) of a transistor. To explore the effectiveness of the proposed technique, a commonsource amplifier is designed. The harmonics of the amplifier are calculated using both the gm/ID technique and Cadence's periodic steady state (PSS) analysis over a wide range of gm/ID. The results indicate a close match (i.e. a discrepancy less than 2 dB from gm/ID=8 to 30) and show that the proposed technique can indeed be incorporated in a gm/ID design flow. I. INTRODUCTIONg m /I D design methodology is a powerful technique that allows designers to quickly size up transistors. The g m /I D design methodology was originally proposed in [2]-[3] and extended to incorporate noise analysis in [4]. A survey of the published literature indicates that there is no prior publication on g m /I D based distortion analysis. This paper describes a procedure to include distortion as part of the g m /I D design flow. Section II describes the underlying principles of g m /I D design flow, introduces a two-dimensional Taylor series approximation, and describes means of obtaining g m /I D based Taylor series coefficients. Section III analyzes the distortion of a common-source amplifier as a means to compare g m /I D based design to Cadence simulation. Section IV describes the limitations of g m /I D based distortion analysis.

Calculation of MOSFET distortion using the transconductance-to-current ratio (g<inf>m</inf>/I<inf>D</inf>)

“…Note that even though the (1/nU T ) 2 pre-factor in (16) decreases with n, the distortion is slightly larger for n = 1.5. This is explained by (6), from which we see that for increasing n, q must decrease to keep g m /I D constant. In any case, the plot is quite insensitive to the exact value of n. Furthermore, and more importantly, the analytical prediction remains close even in strong inversion, even though the constituent transistors suffer from significant mobility degradation.…”

“…In Table I we consider the design of an NMOS differential pair with channel length L = 100 nm, sized to achieve HD 3 = -60 dB and -70 dB for two different input amplitudes (a total of four design scenarios). For each case, we find the required q using (16), and then compute g m /I D from (6). Once g m /I D is determined, the current density I D /W is also fixed and can be found from pre-computed charts or look-up tables [11].…”

“…Two solutions have been proposed to address this issue. The first is to extract the required derivatives using DC sweeps in SPICE [5], [6]. This approach assumes that the simulation model is "well calibrated" and it precludes independent sanity checks that were previously possible with square-law devices.…”

“…Key to this simplification is that the operating point is defined and expressed via the transconductance-to-current ratio (g m /I D ), a quantity that is also useful in the context of general circuit sizing [9]- [11]. In [6], g m /I D was used to define the operating point, but no analytical relationship to the distortion parameters was established.…”

Transconductance/drain current based sensitivity analysis for analog CMOS integrated circuits

“…Building on Jespers' work, we have reported a g m /I D based noise analysis that utilized bias dependent thermal noise coefficient and device noise corner frequency to characterize device noise [2] and a technique to characterize transistor nonlinearity [3].…”