Transient analysis based thermal characterization of die-die interfaces in 3D-ICs

Abstract

In this paper, we present a novel methodology using a thermal test chip to characterize the bulk thermal conductivity and the thermal contact resistance of underfill materials in diedie interfaces of 3D stacks for application-realistic test conditions. Since a silicon chip is used, the thermal properties can be extracted for the same material interfaces (finishing of the Si surface) and the same processing conditions (bonding and temperature profile during curing of the underfill material) as in the intended application. In the proposed methodology, transient thermal measurements obtained using a test chip with integrated heaters and sensors, are combined with thermal finite element simulations to extract the thermal properties.The proposed method is applied to extract the thermal properties and compare the thermal performance of 8 underfill materials. The materials are thermally characterized before and after curing. It is shown that the comparison of the temperature profiles before and after curing can indicate void for matio n or delamination dur ing the curing stage.

Towards Complete Recovery of Circuit Degradation by Annealing With On-Chip Heaters

“…The boundary condition applied in the FEM to mimic these two sets of measurement are: a heat flux that represents the power dissipation in the heater stripes and a constant temperature at the thermochuck. The detailed procedure of the FEM calibration is explained in [22].…”

Thermal modeling of hybrid three-dimensional integrated, ring-based silicon photonic–electronic transceivers

“…12. The reference underfill thermal conductivity is kUF=0.18 W/m-K, 21 a standard value for an unfilled epoxy underfill. A simulation with kUF=0 W/m-K results in a decrease of the effective thermal conductivity from 9.38 to 9.22 W/m-K.…”