Transient Analysis of ESD Protection Circuits for High-Speed ICs

Meiguni, Javad Soleiman; Zhou, Jianchi; Maghlakelidze, Giorgi; Xu, Yang; Izadi, Omid Hoseini; Marathe, Shubhankar; Shen, Li; Bub, Sergej; Holland, Steffen; Beetner, Daryl G.; Pommerenke, David

doi:10.1109/temc.2021.3071644

Cited by 21 publications

(6 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Electrostatic discharge (ESD) protection has always been an important aspect of the reliability of electronic systems [ 3 ]. Moreover, on-chip electrostatic discharge (ESD) protection is necessary for integrated circuits to prevent ESD failures [ 4 ].…”

Section: Introductionmentioning

confidence: 99%

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Chai

Liu

et al. 2023

Micromachines

View full text Add to dashboard Cite

The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC.

show abstract

Section: Introductionmentioning

confidence: 99%

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Chai

Liu

et al. 2023

Micromachines

View full text Add to dashboard Cite

show abstract

“…A conventional measurement technique to characterize protection devices without damaging the devices, is the Transmission Line Pulse (TLP) [5]. Using this generator, some authors have proposed dynamic models for protection devices [4,6,7], but the models are based on measurement using both voltage and current probes, which are frequency limited, and can be used only in time domain. The models are generally SPICE models, which could be difficult to build and implement.…”

Section: Introductionmentioning

confidence: 99%

“…The terms exx are the elements of an error coefficient matrix [E], which are extracted by a series of three measurements on reference loads. The error coefficient matrix [E] is computed according to (7). 9) is error coefficient matrix and [M] a matrix shown in (10).…”

mentioning

confidence: 99%

A fast and efficient Model Extraction Method to predict the transient Response of ESD Protection Devices

Ruffat

Caignet

Boyer

et al. 2022

2022 International Symposium on Electromagnetic Compatibility – EMC Europe

View full text Add to dashboard Cite

ElectroStatic discharge (ESD) protection devices have non-linear and complex behavior that makes system level design robustness predictions complex. To obtain a precise simulation, a model reproducing the turn-on behavior is needed.In this paper we propose a complete measurement and computation setup to get access to an equivalent frequency model of devices under strong pulse injection. To validate our proposed frequency model a comparison of measurements and simulations is performed on passive and linear components first, then on a protection device (TVS).

show abstract

“…LDMOS power transistors have been commonly used as output driver and ESD protection device simultaneously in the smart power technologies [1][2][3]. However, the HV LDMOS doesn't have high ESD robustness after entering its snapback breakdown region.…”

Section: Introductionmentioning

confidence: 99%

Design, Fabrication and Measurement of LDNMOSSCR Devices with Appropriate ESD Protection Window for 18V HV CDMOS Process

2022

Informacije MIDEM

View full text Add to dashboard Cite

Lateral Double Diffused MOSFET (LDMOS) embedded Silicon Controlled Rectifier (SCR) is a normal way to improve the Electro-Static Discharge (ESD) robustness for smart power technologies, but it doesn't always have the proper ESD window for a given application. In this paper, LDNMOS-SCR of four variants structures have been investigated based on a high-voltage (HV) 0.5μm 18V HV CDMOS process with 2D device simulation and silicon verification. Transmission Line Pulse (TLP) testing results demonstrated that those devices successfully elevate the second breakdown current I t2 from original 1.146A to above 3A; source isolated device has a lower trigger voltage V t1 (45.79V) than source non-isolated devices; the holding voltage V h of the four devices is related to their structure, and their holding current I h are all above 800mA, which is big enough to ensure the latch-up immunity under ESD stresses in HV applications. The device with its source isolated from PSUB is the suitable ESD protection device for HV 18V CDMOS technology owning to its strong ESD robustness, low V t1 , small on-resistance Ron and sufficiently big I h .

show abstract

Transient Analysis of ESD Protection Circuits for High-Speed ICs

Cited by 21 publications

References 22 publications

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

A fast and efficient Model Extraction Method to predict the transient Response of ESD Protection Devices

Design, Fabrication and Measurement of LDNMOSSCR Devices with Appropriate ESD Protection Window for 18V HV CDMOS Process

Contact Info

Product

Resources

About