Transistor layout configuration effect on actual gate LER

The role of the gate width in the effects of Line Width Roughness (LWR) on transistor performance is investigated. Two mathematical results regarding the statistical nature of LWR are presented and discussed. Exploiting the implications of these results through a 2D modeling approach, we indicate that, for fixed LWR, transistors with large gate widths seem to mitigate the degradation effects of LWR on transistor performance.

show abstract

Line Width Roughness effects on device performance: The role of the gate width design

Constantoudis

Gogolides

Patsis

2010

2010 27th International Conference on Microelectronics Proceedings

View full text Add to dashboard Cite

show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

Transistor layout configuration effect on actual gate LER

Cited by 1 publication

References 6 publications

Line Width Roughness effects on device performance: The role of the gate width design

Line Width Roughness effects on device performance: The role of the gate width design

Contact Info

Product

Resources

About