Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applications

Zhao, Song; Chatterjee, Amitava; Tang, S. C.; Yoon, Jaegu; Crank, S.; Bu, H.; Houston, T.W.; Sadra, K.; Jain, Amitabh; Wang, Y.; Redwine, D.; Chen, Y.; Siddiqui, S.; Zhang, G.; Laaksonen, Timo; Hall, Carroll Ray; Chang, Simon; Olsen, L.; Riley, Thomas J.; Meek, C.; Hossain, Imran; Rosal, J.; Tsao, A.; Wu, Jeff; Scott, David B.

doi:10.1109/vlsit.2004.1345365

Cited by 17 publications

(5 citation statements)

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“…Researchers have put forth a number of leakage power reduction strategies at the device, circuit, and architectural stages. By scaling the channel length, junction depth, and oxide layer at the device level, the leakage power is decreased [8][9][10]. Researchers have developed fresher transistor structures, such as the Fin-shaped FET (FINFET), which has two or more gates and reduces the subthreshold leakage current and the short channel effect.…”

Section: Leakage Current Minimization Methodologiesmentioning

confidence: 99%

Design of a 6t Sram Cell With Minimal Power Using Cadence Virtuoso

R.Nirmal¹,

P.Nithila²,

K.Jayasudha³

et al. 2023

DRSR

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It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three source biasing techniques are used. At 45 nanometer and 90 nm technology nodes, the three techniques are NMOS diode clamping, PMOS diode clamping, and NMOS-PMOS diode clamping. The implementation of a 6T SRAM cell using the Multiple Threshold CMOS (MTCMOS) technique at 45nm technology is also emphasised in this article. Using the cadence virtuoso tool, the simulation is completed and different power dissipations are examined for 45 nm and 90 nm technologies, respectively, at supply voltages of 0.45 V and 0.9 V. Comparing PMOS clamping to the other two suggested techniques, an average power reduction of 82.19% was observed.

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Section: Leakage Current Minimization Methodologiesmentioning

confidence: 99%

Design of a 6t Sram Cell With Minimal Power Using Cadence Virtuoso

R.Nirmal¹,

P.Nithila²,

K.Jayasudha³

et al. 2023

DRSR

View full text Add to dashboard Cite

show abstract

“…Various leakage power reduction techniques have been proposed by researchers at the device, circuit, and architectural levels. At device level the leakage power is reduced by scaling the channel length, junction depth, oxide thickness [8][9][10].…”

Section: ░ 3 Leakage Current Reduction Techniquesmentioning

confidence: 99%

Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

Banu

Gupta

2022

IJEER

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Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.

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“…There have been large varieties of techniques to deal with leakage power at different levels. In the device level, new material and process techniques have been introduced to control the channel length, oxide thickness, junction depth, and concentration distribution of transistors (Steegen et al, 2005;Koh et al, 2003;Zhao et al, 2004). An optimized Ni-Si process, a high angle, and low dose halo implants contribute to reduced junction leakage and gate-induced drain leakage (GIDL) current (Steegen et al, 2005).…”

Section: Leakage Power Reduction Technologiesmentioning

confidence: 99%

Leakage power reduction techniques of 45 nm static random access memory (SRAM) cells

Singh¹

2011

Int. J. Phys. Sci.

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As the technology scales down to 90 nm and below, static random access memory (SRAM) standby leakage power is becoming one of the most critical concerns for low power applications. In this article, we review three major leakage current components of SRAM cells and also discuss some of the leakage current reduction techniques including body biasing, source biasing, dynamic V DD , negative word line, and bit line floating schemes. All of them are achieved by controlling different terminal voltages of the SRAM cell in standby mode. On the other hand, performance loss occurs simultaneously with leakage saving. To validate the effectiveness of low power techniques, the leakage current, static noise margin, and read current of SRAM cells, based on the UMC 45 nm complementary metal-oxide-semiconductor (CMOS) process with leakage current reduction techniques has been simulated. The results indicate that by using the dynamic V DD and source biasing schemes, greater leakage suppressing capability, although with a higher performance loss, can be obtained. Therefore, the SRAM cell optimization scheme must consider the trade-off between power consumption and speed performance.

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Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applications

Cited by 17 publications

References 0 publications

Design of a 6t Sram Cell With Minimal Power Using Cadence Virtuoso

Design of a 6t Sram Cell With Minimal Power Using Cadence Virtuoso

Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

Leakage power reduction techniques of 45 nm static random access memory (SRAM) cells

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