Transmission gate-based approximate adders for inexact computing

Yang, Zhixi; Han, Jie; Lombardi, Fabrizio

doi:10.1109/nanoarch.2015.7180603

Cited by 73 publications

(52 citation statements)

References 14 publications

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“…Recent research of approximate arithmetic circuits is concentrated on reduction in transistor count as well as critical path as compared with the accurate FAs. Recently, two transmission gate‐based inexact FAs, TGA1 and TGA2, are presented which consist of 16 and 22 transistors, respectively. The output carry of TGA1 follows directly one of the input B.…”

Section: Review Of Previous Workmentioning

confidence: 99%

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A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications

Goyal¹,

Ubhi

Raj

2019

Circuit Theory & Apps

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Summary This paper presents a highly stable, low leakage inexact full adder (FA) which is based on top gate carbon nanotube field effect transistors (TG‐CNTFET) for motion detector applications. Inexact arithmetic circuits are highly accepted in low power multimedia applications. Circuit level metrics, ie, average power, propagation delay, power‐delay product (PDP), and leakage power dissipation as well as application level metric such as peak signal to noise ratio (PSNR) are considered to compare the performance of proposed inexact FA. All the simulations are performed using HSPICE tool with Stanford 32‐nm TG‐CNTFET model. The operating frequency used for simulation is 1‐Ghz with 0.9‐V supply voltage. Proposed inexact FA successfully achieve manifold reduction in leakage power as well as consume 89.2% lesser energy as compared with latest existing inexact FA while having other parameters in acceptable range. Simulations using MATLAB show satisfactory image quality and PSNR value for motion detection applications. The effect of variations in voltage and temperature on leakage power is also presented which confirms stability of the proposed circuit.

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Section: Review Of Previous Workmentioning

confidence: 99%

“…Recently, two transmission gate-based inexact FAs, TGA1 and TGA2, 13 are presented which consist of 16 and 22 transistors, respectively. The output carry of TGA1 follows directly one of the input B.…”

Section: Review Of Previous Workmentioning

confidence: 99%

A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications

Goyal¹,

Ubhi

Raj

2019

Circuit Theory & Apps

View full text Add to dashboard Cite

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“…An expression for variance of error of AMA 1-5 adders [4] and Lower part OR adder (LOA) [5] is obtained in [11] empirically by regression assuming uniform inputs, and heuristics are used to solve the approximationlevel optimization problem. In [12], AMA 1-5 adders and Transmission Gate based Approximate adders TGA I-II [13] are considered. An expression for mean square error (MSE) is obtained assuming that the distribution of inputs and error are uniform.…”

Section: Introductionmentioning

confidence: 99%

ErrorModelingLPAA.pdf

Dharmaraj¹,

Vasudevan²,

Chandrachoodan³

2019

Preprint

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Approximate circuit design has gained significance in recent years targeting error tolerant applications. In this paper, we consider the problem of minimizing the power for a given accuracy, in a signal processing application with accurate adders replaced by low-power approximate adders. We first demonstrate that the commonly used assumption that the inputs to the adder are uniformly distributed results in an inaccurate prediction of error statistics for multi-level circuits. To overcome this problem, we propose the use of parameterized error models for adders, with input static probabilities as parameters. The static probability computation in our work considers not just the functionality of the adder but also its position in the circuit, functionality of its parents and the number of approximate bits in the parent blocks. This parameterized error model can be incorporated in any optimization framework. We demonstrate up to 6.5 dB improvement in the accuracy of noise power prediction when the proposed model is used to optimize an 8 × 8 DCT.

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“…These designs cut the carry propagation chain to induce some errors to approximately calculate the results. Another type for reducing the critical path delay and power consumption is to approximate functional behavior by implementing a different Boolean function from a conventional adder, e.g., [6,7,8,9].…”

Section: Introductionmentioning

confidence: 99%

An analytical framework for error modeling of approximate adders

Yang

Xing

et al. 2016

IEICE Electron. Express

Self Cite

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Approximate computing has drawn recent attention as it can reduce power without significantly sacrificing the output quality for arithmetic operations in error-resilient applications. However, the error characteristics evaluation often depends on time consuming random simulation and estimation. In this paper, a formal framework of evaluating approximate adders is proposed based on a theoretical model. The proposed framework can accurately measure mean squared error (MSE) and mean absolute error (MAE) without using functional simulations. An approach has been adopted to estimate the final PSNR value in terms of MSE and MAE for DCT-IDCT image compression system. Experimental results have validated the accuracy and usefulness of the framework. Keywords: approximate computing, error modeling and analysis, approximate adder, squared error, absolute error Classification: Integrated circuits

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Transmission gate-based approximate adders for inexact computing

Cited by 73 publications

References 14 publications

A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications

A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications

ErrorModelingLPAA.pdf

An analytical framework for error modeling of approximate adders

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