Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

Abstract

e ability to map instructions running in a microprocessor to a recon�gurable processing unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and ensures code and possibly performance portability. In this work, we focus on the mapping of loop-based instruction traces (called Megablocks) to RPUs. e proposed approach considers offline partitioning and mapping stages without ignoring their future runtime applicability. We present a toolchain that automatically extracts speci�c trace-based loops, called Megablocks, from MicroBlaze instruction traces and generates an RPU for executing those loops. Our hardware infrastructure is able to move loop execution from the microprocessor to the RPU transparently, at runtime, and without changing the executable binaries. e toolchain and the system are fully operational. ree FPGA implementations of the system, differing in the hardware interfaces used, were tested and evaluated with a set of 15 application kernels. Speedups ranging from 1.26× to 3.69× were achieved for the best alternative using a MicroBlaze processor with local memory.

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

“…Table 2 presents average number of clock cycles required to process one DFG node, in orders of magnitude, for nine modulo scheduling approaches found in literature: DRESC [27]; EMS [32]; RF [9]; RAM [29]; MSPR [11]; G -Minor [8]; EPImap [14]; REGIMap [16]; MS JIT [10]. Moreover, Table 2 presents our BT MS approach and a trace-based binary translation (TBT) proposed in [4]. The number of cycles were obtained from the respective references, with exception of DRESC, which time results were based on information reported in [8,29].…”

“…However, the MS JIT [10] time does not include the DFG extraction and binary translation. Moreover, the TBT [4] requires three orders of magnitude more efforts than our BT MS, which also includes a binary translation in software.…”

“…Other solutions [4,8,9,14,16,29,32] emerged in an attempt to reduce compile-time by improving the mapping algorithm. In [32], Park et al, proposed a modulo scheduling for CGRA, called EMS (Edge-centric Modulo Scheduling), that focuses on routing efficiency as the primary goal, since routing is a very time-consuming step in CGRAs.…”

“…In spite of that, for a 4x4 mesh CGRA and varying number of local registers, the compilation time is still in order of thousands of seconds. [4] proposes an approach that combines offline partitioning and mapping with online reconfiguration to accelerate loops in a reconfigurable coprocessor. The mapping algorithm searches for loop-based instruction traces, called megablocks.…”

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

“…Our previous work Bispo et al [2013aBispo et al [ , 2013b presented a transparent binary acceleration system based on automatically generated coarse-grained RPUs (Reconfigurable Processing Units). In our system, a GPP is aided by a tailored coprocessor able to transparently accelerate the execution of repetitive sequences of GPP instructions.…”