Transport and Noise Properties of sub-100-nm Planar Nb Josephson Junctions with Metallic Hf - Ti Barriers for nano-SQUID Applications

Abstract

We analyze electric transport and noise properties at 4.2 K of self-shunted superconductor-normal metal-superconductor (SNS) sandwich-type Josephson junctions, comprising Nb as the superconductor and Hf-Ti as the normal conducting material, with lateral dimensions down to approximately 80 nm. The junctions are fabricated with an optimized multilayer Nb technology based on nanopatterning by electron-beam lithography and chemical-mechanical polishing. The dependence of transport properties on the junction geometry (lateral size and barrier thickness d Hf-Ti) is studied, yielding a characteristic voltage V c up to approximately 100 μV for the smallest d Hf-Ti = 17 nm. The observed small hysteresis in the current-voltage curves of devices with high V c and large size can be attributed to self-heating of the junctions and fitted with an extended version of the resistively shunted junction model. Measurements of voltage noise of single junctions are consistent with the model including self-heating effects. The potential of our technology for further miniaturization of nanoscale superconducting quantum interference devices and for the improvement of their performance is discussed.

Fabrication Process for Deep Submicron SQUID Circuits with Three Independent Niobium Layers

“…In addition, a CMP step is used to planarize the SiO 2 layer between the first and second independent Nb layer. Both technologies are available at the clean room center at PTB Braunschweig and have been applied before in the fabrication of JJ-based circuits [ 29 , 30 , 33 ]. Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 illustrate the deposition and patterning steps (we note that the layer thicknesses are not to scale).…”

“…The trilayer consists of a 160 nm Nb base layer, 20 to 22 nm Hf wt50% Ti wt50% (HfTi) and a 200 nm Nb top layer for six wafers, which were fabricated for this paper. As mentioned above, the HfTi thickness can be adjusted, to obtain a desired critical current density, in a typical range from 17 to 26 nm [ 33 ]. To define the deep sub-µm JJs, a 30 nm Al hard mask is patterned by lift-off, using EBL with PMMA as a positive resist.…”

“…Additionally, data of single JJs with nominal widths of 200 nm from [ 33 ] are shown for comparison. For those, j c is calculated using the effective area (considering deviations from the nominal area due to the patterning process and due to edge damage).…”

“…For our JJs, the expression [ 46 ] j c = j c0 · exp[− d HfTi /ξ N ] can be used [ 33 ] to describe the dependence of the critical current density on the HfTi barrier thickness, where ξ N is the coherence length in the normal conducting barrier. In ref.…”

“…During the last years, it has been shown that the above-mentioned requirements can be met by fabricating devices based on trilayer JJs with superconducting (S) Nb electrodes and a normal conducting (N) HfTi barrier, using nanopatterning by electron beam lithography (EBL) and chemical–mechanical polishing (CMP) [ 30 , 31 ]. The critical current density of SNS JJs with HfTi barriers can be adjusted over a very wide range by the thickness of the N layer up to j 0 ≈ 1 MA/cm 2 at temperature T = 4.2 K. Furthermore, lateral JJs sizes down to 80 nm diameter have been achieved [ 32 , 33 ]. We note that by the implementation of intrinsically shunted SNS JJs we avoid space-consuming external shunting resistors of the JJs in the circuit.…”